Infineon C166S V1 SubSystem, Руководство пользователя

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User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
User’s Manual 12-9 V 1.6, 2001-08
Timer 3 in Timer Mode
Timer Mode for core Timer T3 is selected by setting bitfield T3M in register T3CON to
‘000
B
’.
A block diagram of T3 in Timer Mode is shown in Figure 12-4 .
In this mode, T3 is clocked with the module clock f
clk
divided by a programmable
prescaler block, controlled by bitfield T3I and BPS1. The input frequency f
T3
for Timer
T3 and its resolution
r
T3
are scaled linearly with lower module clock frequencies, as can
be seen from the following formula:
Note: <BPS1> represents the prescaler value of the prescaler part controlled by bitfield
BPS1. For the values, see the bit description in register T3CON.
Table 12-2 Timer 3 Input Parameter Selection: Timer and Gated Timer Modes
T3I Prescaler for f
clk
(BPS1 = 00)
Prescaler for f
clk
(BPS1 = 01)
Prescaler for f
clk
(BPS1 = 10)
Prescaler for f
clk
(BPS1 = 11)
000 8 4 32 16
001 16 8 64 32
010 32 16 128 64
011 64 32 256 128
100 128 64 512 256
101 256 128 1024 512
110 512 256 2048 1024
111 1024 512 4096 2048
Table 12-3 Example for Timer 3 Frequencies and Resolutions
f
clk
[MHz] T3I BPS1 f
T3
[KHz] r
T3
[µs]
40 7 10 9.77 102.4
40 0 01 10000 0.1
50 0 00 6250 0.16
50 4 11 195.31 5.12
50 7 10 12.20 81.97
f
T3
=
f
clk
<BPS1> * 2
<T3I>
r
T3
[ms] =
f
clk
[MHz]
<BPS1> * 2
<T3I>