IBM 7013 J Series, Руководство оператора

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SystemGuard Test Groups
A-19
Interrupt Tests Group
These tests are performed by the BUMP as well as the processors. They are launched at
Power On and under control of Off Line Test Monitor. They collectively check the interrupt
system. The following tests are available under this group.
BUMP To CPU Interrupt Test
This test is performed jointly by the BUMP and the processor. It contains one sub-test which
checks the capability of the BUMP to generate an interrupt request to one CPU. The errors
can be either detected by the BUMP or by the processor. They are suitably displayed on the
console. This test also checks the following h/w parts:
1. Processor Interrupt Capability
2. Interrupt Management of SSGA.
3. Control Logic PLD.
CPU To BUMP Interrupt Test
This test is performed jointly by the BUMP and the processor. It contains one sub-test which
checks the capability of the processor to generate an interrupt request to BUMP. The errors
can be either detected by the BUMP or by the processor. They are suitably displayed on the
console. This test also checks the following h/w parts:
1. BUMP Interrupt Capability
2. Interrupt Management of SSGA.
3. Control Logic PLD.
UART To CPU Interrupt Test
This test is performed by the processor. It has a sub-test which checks the capability of the
Super-I/O Async line to generate an interrupt request to the CPU. The following h/w parts
are checked by the test:
1. Processor Interrupt Capability
2. SSGA Interrupt Management
3. PLD Control Logic
4. Super-I/O Interrupt Mechanism
Whenever an error is detected by the processor, an error message giving the details of the
error is displayed.
CPU To CPU Interrupt Test
This test checks the capability for a CPU to interrupt another CPU. The two CPUs of the
same card are used (the capability for a CPU to interrupt a CPU located an another CPU
card is not used in this test).
TOD To BUMP Interrupt Test
This test is launched and performed by the BUMP. It has one sub-test to check the interrupt
generating mechanism of the TOD chip.
This test checks the BUMP and TOD h/w during the process. TOD internal registers are not
modified during the test. This test displays error messages during the test if an error is
detected.