IBM 7013 J Series, Руководство оператора

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Operator Guide
A-10
Super I/O and UART Access Test
This test checks the accessibility of the Super I/O chip from the processors. They don’t
check the functional aspects of the Super I/O chip (this is done by the BUMP directly). The
following sub-tests are available under this test:
Super I/O UART 1 Access Test
Specific values are written and read in the data register scratch
SCR. The read values are compared with the written values.
Super I/O UART 2 Access Test
Specific values are written and read in the data register scratch
SCR. The read values are compared with the written values.
16550 UART Access Test
This test writes and reads specific values. These operations are
done on SCR register. Comparison is also done. The read values
are compared with the written values.
Floppy disk Controller Access Test
The data register scratch DOR, is written with specific values. Read
and compare operations are conducted. The read values are
compared with the written values.
Bidirectional Parallel Port Access Test
This test writes and reads specific values. These operations are
done on DTR register. Comparison is done. The read values are
compared with the written values.
Flash EPROM Access Test
This test calculates the checksum of the different parts of the Flash EPROM and compares
the obtained result to the registered result.
EPROM Access Test
This test calculates the checksum of the different parts of the EPROM and compares the
obtained result to the registered result.
TOD Access Test
This test is conducted to check the accessibility of the TOD chip from the processors. It has
two sub-tests. All the registers which are used during the operation are saved in the
beginning and are restored at the end.
Embedded RAM Test Specific values are written, read and compared in this test.
TOD Registers Test This test operates on SEC_COMP_RAM register. It writes and
reads specific values. Values are compared and if a mismatch is
detected, an error message will be generated.
I
ON-2 REGS TEST
This test is performed by all the processors and it checks the accessibility from the
processor to the IONIAN2 and DMA slave chips. Following h/w parts are checked.
•
DCB ASIC
•
IONIAN 2 ASIC
Initial Values Test
This test checks the initial values of the IONIAN and SSGA ASICs. It is only run at PON
time.