IBM 7012 G Series, Руководство по обслуживанию

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SystemGuard Test Groups
A-5
NVRAM Test
This test checks the accessibility of NVRAM bytes. It contains the following sub-tests:
NVRAM Data Lines Access Test
This test saves the first NVRAM byte. Then a read / write operation
is done word by word. It restores the first NVRAM byte.
NVRAM Address Lines Access Test
This test reads, writes and compares 2 NVRAM addresses. The
NVRAM addresses involved in this test are saved before testing
and restored after testing.
Stack Area Read / Write Test
This test is for all stack area bytes. It saves the byte, conducts
read/write operation and compares the written word with the read
word. Then it restores the byte.
Permanent Data Areas Test
This test is performed for all permanent data areas with an
associated check sum. Data area check sum is calculated and is
compared with the registered check sum.
EPROM Test
This test is meant to check the EPROM contents. It contains the following sub-tests.
Check-Sum Test During this test, EPROM is divided in to different areas and CRC is
found for each area. Then this calculated CRC is compared with the
registered CRC.
TOD Test
This test checks the access to the Time Of Day chip and it s functionalities. All values are
saved and restored. It contains the following sub-tests:
MSR register test This test checks the PS and RS bits of the MSR registers by the
way of write/read operations.
Internal RAM Test In this test MSR register is initialized and RAM content checking is
done by the way of write / read operations.
Wake-up Mechanism Test
This test includes “Seconds” register reading, wake-up mechanism
activation, MSR reading.
Floppy Disk Controller Test
This test checks the accessibility to the Super I/O chip and the Floppy Disk Controller
embedded in the Super I/O chip. It contains the following sub-test.
DOR Register Test
This test writes, reads and compares a 1 among the 0 bits in the DOR register.
BPP Controller Test
This test checks the accessibility to the Super I/O chip and the Bi-directional Parallel Port
embedded in the Super I/O chip. These tests don’t access the hardware part related to BPP.
It contains the following sub-tests:
Addressing Register Test
This test writes, reads and compares different values in DTR and
CTR registers. It saves and restores the CTR register value.