HP X Class 500/550MHz, Справочное руководство

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Chapter 2 39
System Board
Chipset
Host Bridge Interface
The Pentium III Xeon processor supports a second level cache via a Dual Independent Bus
(DIB). All control for the L2 cache is handled by the processor. The Host Bridge provides
bus control signals and address paths for transfers between the processors FSB (host bus),
PCI bus, AGP and main memory. The Host Bridge supports a 4-deep in-order queue (i.e.,
supports pipelining of up to four outstanding transaction requests on the host bus). Due to
the system concurrency requirements, along with support for pipelining of address
requests from the host bus, the Host Bridge supports request queueing for all three
interfaces (Host, AGP and PCI).
Host-initiated I/O cycles are decoded to PCI, AGP or PCI configuration space.
Host-initiated memory cycles are decoded to PCI, AGP (prefetchable or non-prefetchable
memory space) or DRAM (including AGP aperture memory). For memory cycles (Host, PCI
or AGP initiated) that target the AGP aperture space in DRAM, the Host Bridge translates
the address using the AGP address translation table. Other host cycles forwarded to AGP
are defined by the AGP address map.
PCI and AGP initiated cycles that target the AGP graphics aperture are also translated
using the AGP aperture translation table. AGP initiated cycles that target the AGP
graphics aperture mapped in main memory do not require a snoop cycle on the Host bus,
since the coherency of data for that particular memory range will be maintained by the
software.
The chip can support one or two Pentium III Xeon processors, at up to 100 MHz FSB clock
frequency. Refer to the section “Host Bus” in this chapter for a description of the devices on
the Host Bus.
PCI Bus Interface
The Host Bridge/Controller provides the interface to a PCI bus interface operating at 33
MHz. This interface implementation is compliant with PCI Rev 2.1 Specification,
supporting up to five external PCI masters in addition to the PIIX4E Bridge chip and the
Adaptec AIC 7880 16-bit SCSI controller. The PCI-to-DRAM interface can reach a transfer
rate of over 100 MBytes/sec for streaming reads and over 120 MBytes/sec for streaming
writes.
Sequential PL-to-PCI memory write cycles are translated into PCI zero wait state burst
cycles. The maximum PCI burst transfer can be between 256 bytes and 4 KB. The chip
supports advanced snooping for PCI master bursting, and provides a pre-fetch mechanism
dedicated for IDE read.
Refer to the section “Devices on the PCI Bus” in this chapter for a description of the devices
on the PCI Bus.
AGP Bus Interface
A controller for the AGP (Accelerated Graphics Port) slot is integrated in the Host
Bridge/Controller. The AGP Bus interface is compatible with the Accelerated Graphics
Port Specification, Rev 1.0, and it can support up to 133 MHz data transfer rates. The Host
Bridge/Controller supports only a synchronous AGP interface, coupling to the host bus
frequency. AGP characteristics are described in detail in the section “Accelerated Graphics
Port (AGP) Controller” in this chapter.