
Rev. 1.00
248 of 486
July 31, 2018
32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
14 Pulse W
idth Modulator (PWM)
14 Pulse W
idth Modulator (PWM)
Features
▄
16-bit up / down auto-reload counter
▄
16-bit programmable prescaler that allows division of the counter clock frequency by any factor
between 1 and 65536
▄
Up to 4 independent channels for:
●
Compare Match Output
●
Generation of PWM waveform – Edge and Center-aligned Mode
●
Single Pulse Mode Output
▄
Synchronization circuit to control the timer with external signals and to interconnect several
timers together
▄
Interrupt generation with the following events:
●
Update event
●
Trigger event
●
Output compare match event
▄
PWM Master / Slave mode controller
Functional Descriptions
Counter Mode
Up-Counting
In this mode the counter counts continuously from 0 to the counter reload value, which is defined
in the CRR register, in a count-up direction. Once the counter reaches the counter reload value,
the Timer Module generates an overflow event and the counter restarts to count once again from
0. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register
should be set to 0 for the up-counting mode.
When the update event is generated by setting the UEVG bit in the EVGR register to 1, the counter
value will also be initialized to 0.
CK_PSC
CNT_EN
F3
F4
F5
CK_CNT
F2
F5
CNTR
CRR Shadow
Register
CRR
36
F5
36
0
1
0
1
PSCR
PSCR Shadow
Register
0
0
1
0
1
0
1
0
0
1
2
3
PSC_CNT
Counter Overflow
Update Event Flag
Software clearing
Write a new value
1
Update the new value
Figure 64. Up-counting Example