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HARRIS
888-9058-001
WARNING: Disconnect and lockout AC primary power prior to servicing
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microprocessor. The diagnostic LEDs flash in a regular sequence during normal
operation.
5.5.1.4 RS232, Watch Dog and Front Panel Interface (Sheet 4)
(Sheet 4 of the drawing shows several interfaces used in the controller)
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BDM is Background Debug Mode provides for emulation and debugging for the 376
microcontroller. There is no user usage of this connection.
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U43, the EEPROM, is a 128/256K, SPI Bus Serial high speed EEPROM. This is used
for storing the program for the 376microcontroller.
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U100 is a watchdog timer IC. A watchdog timeout occurs if it's input has not been
toggled within 1.6 seconds. A master reset occurs on watchdog time-outs unless the
Watchdog Disable line on the module interface is held above 4.5v. The watchdog
input (kick watchdog) shall be made available on the module interface. This line may
be monitored to ensure the microprocessor is still alive and the reset line on the module
interface may be monitored for when a reset is taking place. There is a RESET
switch S2 that can force a reset at any time.
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U104 is the RS232 microprocessor interface for use in communication with exciters.
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The front panel is connected to the main controller using J7, the protection and
opamp buffering interface with the CPLD inputs.
5.5.1.5 Controller Analog Sense (Sheet 5)
Sheet 5 includes four analog multiplexer / demultiplexer CMOS integrated circuits.
These select one of eight inputs to an output. These chips become four of the analog
inputs to the micro module.
5.5.1.6 CPLD (Sheet 6)
The Controller will have an XC95288 to act as memory mapped I/O and perform critical
functions in the event that the Micro Module fails. The Micro Module will interface to
the CPLD through /CS2, /CS7, address lines 19 down to 16 and the data lines 15 down
to 8.
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Critical Life Support Functionality
The critical life support functionality occurs when an on board watchdog is triggered as
a result of an unresponsive Micro Module.
The CPLD will control the transmitter on/off state and under life support conditions will
respond to the front panel and the customer remote commands. The outputs of the
detectors will be compared to thresholds set in EEPots by the Micro Module before the
fault status is passed to the CPLD. This will allow the CPLD to mute the transmitter
during a forward or reflected overdrive.
The CPLD will also monitor all discrete external customer I/O, the front panel switch
board I/O, and the interlocks, so that the controller can maintain critical functionality
during the event of a micro failure.