Publication No. SBC330-0HH/3
FPGA Registers 71
6.20 Scratch Registers
The
SBC330
has
two
16
‐
bit
scratch
registers
for
user
applications.
These
are
read
‐
write
registers
and
are
initialized
to
0x0000.
Chip
Select
CS2
Offset
0x0064
and
0x0068
LAD Bit
Reg Bit
R/W
Description
Reset Value
15
0
R/W
User defined bit 0
0
14
1
R/W
User defined bit 1
0
13
2
R/W
User defined bit 2
0
12
3
R/W
User defined bit 3
0
11
4
R/W
User defined bit 4
0
10
5
R/W
User defined bit 5
0
9
6
R/W
User defined bit 6
0
8
7
R/W
User defined bit 7
0
7
8
R/W
User defined bit 8
0
6
9
R/W
User defined bit 9
0
5
10
R/W
User defined bit 10
0
4
11
R/W
User defined bit 11
0
3
12
R/W
User defined bit 12
0
2
13
R/W
User defined bit 13
0
1
14
R/W
User defined bit 14
0
0
15
R/W
User defined bit 15
0
