Publication No. SBC330-0HH/3
FPGA Registers 63
6.12 ID Register
All
boards
are
assigned
an
ID.
The
ID
for
the
SBC330
is
0x30.
This
fixed
value
is
held
in
this
register.
6.13 Flash Control Register
The
Flash
Control
Register
allows
the
SBC330
to
read
the
state
of
the
Flash
Control
jumpers.
See
Section
4.3
for
more
information
on
the
operation
of
the
Flash
jumpers.
The
names
of
the
jumper
signals
in
this
document
relate
to
the
net
name
that
they
connect
to
(user
manuals
may
describe
these
differently.)
• CPLD_JMP1
selects
AMP
or
SMP
mode
• CPLD_JMP2
overrides
any
software
setting
of
unlocking
the
password.
Fitting
this
jumper
locks
the
password
registers
and
the
boot
area
• FLASH_BOOT_SEC1
and
FLASH_BOOT_SEC2
form
binary
combinations
that
determine
the
address
of
the
boot
Flash
areas
as
described
in
Section
4.3
The
initial
value
depends
on
jumper
settings.
Fitted
jumpers
are
indicated
by
a
‘1’,
(which
is
opposite
to
the
signal
level).
The
Password
Control
bit
is
low
(‘0’),
so
that
the
password
is
not
visible
at
power
up.
Page
mode
is
disabled
(low
‐
‘0’).
Page
mode
is
not
implemented
for
the
initial
release.
Page
mode
bits
are
initialized
to
0000
b
.
Page
Mode
functions
(for
very
large
Flash
memory
sizes)
are
unlikely
to
be
implemented
on
the
SBC330.
If
they
are,
the
page
mode
control
will
be
added
into
this
register.
Chip
Select
CS2
Offset
0x0064
and
0x0068
Reset
value
0x30
‐
Defines
the
SBC330
Product
LAD Bit
Reg Bit
R/W
Description
Reset Value
15
0
R
ID reg bit 0
0
14
1
R
ID reg bit 1
0
13
2
R
ID reg bit 2
0
12
3
R
ID reg bit 3
0
11
4
R
ID reg bit 4
1
10
5
R
ID reg bit 5
1
9
6
R
ID reg bit 6
0
8
7
R
ID reg bit 7
0
Chip
Select
CS2
Offset
0x0044
Reset
value
Depends
on
jumper
settings
