GE SBC330 3U VPX, Справочник по аппаратуре

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52 SBC330 3U VPX Single Board Computer Publication No. SBC330-0HH/3
6.4 BIT and User LEDs Register
The SBC330 has two red and two green BIT LEDs located on the front edge rear
side of the PCB. There are two of each BIT LEDs because each core is required to
boot and pass MPE regardless of whether the board is in AMP or SMP operation.
A ‘1’ in a register bit turns the associated LED on.
NOTE
The associated signal lines from the FPGA are low when the LEDs are lit; the FPGA sinks the current.
The default released FPGA code leaves the red BIT Fail LEDs turned on and the
green User LEDs turned off. The initialized register value therefore reads 0x000C.
6.5 GPIO Registers
The SBC330 has 8 bits of GPIO. These lines can be set up as either inputs or
outputs but not tristate drivers. The actual signal lines are protected as inputs to
the FPGA through a quick ‐ switch in ‐ line FET device, which prevents over ‐ voltage
being seen at the FPGA pins. This device generates no extra current drive
capacity, so GPIO lines should only be connected to a maximum of two 3V3 TTL/
CMOS loads. By default, the FPGA uses 3V3 CMOS levels for GPIO.
At power up, all the GPIO lines default to inputs, so the reset value of the GPIO
Input register depends on external circuit conditions. Reads and writes to the
register are synchronous to the local clock bus, so fast operations generate
synchronous timing on the GPIO pins at a maximum frequency of ½ the local bus
speed, which is 100 MHz for 400 MHz platforms or 133 MHz for 533 MHz
platforms.
The GPIO Invert register is used for cases where an external board uses an active
high signal that needs to be sensed by the SBC330 as an interrupt. The interrupt
mechanism is set up for active ‐ low interrupt signals, so the external signal needs
to be inverted for correct operation.
The GPIO Direction register controls individual bits to be either inputs or outputs.
Once selected as an output, the SBC330 drives the I/O line to the value set in the
GPIO Output register. To prevent glitches on outputs, set the GPIO Output
register to the logic level required before selecting the GPIO bit as an output.
The GPIO Output register controls individual GPIO lines. Lines selected as inputs
ignore the GPIO Output register values.
Chip Select CS2
Offset 0x0010
LAD Bit Reg Bit R/W Description Reset Value
15 0 R/W User1 LED (green) 0x0
14 1 R/W User2 LED (green) 0x0
13 2 R/W BIT_1_LED (red) 0x1
12 3 R/W BIT_2_LED (red) 0x1