Publication No. SBC330-0HH/3
FPGA Registers 49
6.2.2 Interrupt Mask register
This
register
defaults
to
0x0000
(all
interrupts
masked)
at
power
up.
Writing
a
‘1’
in
this
register
unmasks
the
interrupt
in
the
Interrupt
register,
and
to
the
CPU.
Software
should
unmask
the
CPU_HOT_ALERT
and
the
THERMAL_SHUTDOWN
signals,
which
indicate
the
CPU
temperature.
Unless
software
unmasks
these
bits,
the
processor
will
not
know
if
it
is
in
danger
of
overheating
and
to
store
any
useful
information.
The
THERMAL_SHUTDOWN
signal
actually
cuts
the
power
to
the
board’s
main
ICs
by
signaling
to
the
Lattice
Power
Manager
to
turn
off
most
of
the
supplies.
The
5V
input
voltage
and
the
P3V3_LIN
rail
remain
powered
to
maintain
RTC
and
BMM
functions.
Chip
Select
CS2
Offset
0x0004
LAD Bit
Reg Bit
R/W
Interrupt Source
Reset Value
23
0
R/W
GPIO bit (0)
0
22
1
R/W
GPIO bit (1)
0
21
2
R/W
GPIO bit (2)
0
20
3
R/W
GPIO bit (3)
0
19
4
R/W
GPIO bit (4)
0
18
5
R/W
GPIO bit (5)
0
17
6
R/W
GPIO bit (6)
0
16
7
R/W
GPIO bit (7)
0
15
8/0 orig
R/W
Ethernet PHY on ETSEC 1
0
14
9
R/W
Ethernet PHY on ETSEC 3
0
13
10
R/W
USB INT A
0
12
11
R/W
USB INT B
0
11
12
R/W
USB INT C
0
10
13
R/W
CPU_HOT_ALERT
0
9
14
R/W
THERMAL SHUTDOWN
0
8
15
R/W
PEX8114_INT_A
0
7
16
R/W
EXTERNAL_INT (if enabled)
0
6
17
R/W
REAL TIME CLOCK INT
0
5
18
R/W
WATCHDOG 0 INTERRUPT
0
4
19
R/W
WATCHDOG 1 INTERRUPT
0
3
20
R/W
(reserved for expansion)
0
2
21
R/W
(reserved for expansion)
0
1
22
R/W
(reserved for expansion)
0
0
23
R/W
(reserved for expansion)
0
