Publication No. SBC330-0HH/3
FPGA Registers 61
6.11.1 Core 0 and Core 1 semaphore registers
The
Core
Semaphore
registers
are
simple
16
‐
bit
read/write
registers
that
can
only
be
written
to
if
the
Hardware
Exclusive
Access
Semaphore
Register
has
its
LSB
set
to
1,
indicating
that
a
process
has
set
it.
Software
determines
the
use
of
the
bits
–
they
are
not
dedicated
to
any
particular
resource
or
function.
This
register
initializes
to
0x0000.
Chip
Select
CS2
Offset
0x0074
(Core
0)
and
0x0078
(Core
1)
LAD Bit
Reg Bit
R/W
Description
Reset Value
15
0
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 0
0x0
14
1
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 1
0x0
13
2
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 2
0x0
12
3
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 3
0x0
11
4
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 4
0x0
10
5
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 5
0x0
9
6
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 6
0x0
8
7
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 7
0x0
7
8
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 8
0x0
6
9
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 9
0x0
5
10
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 10
0x0
4
11
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 11
0x0
3
12
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 12
0x0
2
13
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 13
0x0
1
14
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 14
0x0
0
15
R/W if HWA Sem taken
Core 0/Core 1
Semaphore bit 15
0x0