Publication No. SBC330-0HH/3
FPGA Registers 57
6.8 Core Multiplier Register
The
Core
Multiplier
in
the
8641D
takes
the
platform
frequency
as
its
source
and
multiplies
it
by
a
selectable
ratio
to
produce
the
core
frequency.
This
ratio
ranges
from
2:1
to
4.5:1
in
steps
of
0.5.
This
register
is
loaded
at
power
‐
up
from
a
configuration
resistor
setting.
The
register
is
connected
to
the
pins
LDP[0:3]
and
LA[27],
and
drives
during
power
‐
on/reset.
The
register
is
‘Sticky’
through
a
front
‐
panel
hard
reset,
i.e.
the
core
speed
can
be
adjusted
by
writing
to
this
register
and
asserting
the
Reset
signal.
The
register
returns
to
its
default
following
a
power
cycle.
The
meaning
of
the
bits
is
reproduced
here
from
the
8641D
specification:
Chip
Select
CS2
Offset
0x0024
LAD Bit
Reg Bit
R/W
Description
Reset Value
15
0
R/W
DP(0)
Variant dependent
14
1
R/W
DP(1)
Variant dependent
13
2
R/W
DP(2)
Variant dependent
12
3
R/W
DP(3)
Variant dependent
11
4
R/W
ADD_27
Variant dependent
Table 6-4
Signal
Binary
Platform Clock (MPX
Bus) Multiplier
Comments
LDP[0:3], LA27
0_1000
2:1
0_1100
2.5:1
Default for 400 MHz/1 GHz boards
1_0000
3:1
Default for 500 MHz/1.5 GHz boards
1_1100
3.5:1
1_0100
4:1
0_1110
4.5:1
