Publication No. SBC330-0HH/3
Functional Description 35
The
FPGA
is
used
to
form
several
registers
that
are
visible
to
the
processor
on
the
local
bus
and
are
accessed
using
the
CS2
chip
select
line
of
the
M8641D.
In
the
default
VxWorks
release,
the
registers
are
located
at
address
0xFC00
0000,
but
the
location
of
these
registers
in
memory
space
is
defined
solely
on
the
CS2
BAR
and
so
they
are
movable.
5.6 Local Bus Control FPGA
The
Local
Bus
Control
FPGA
is
a
Lattice
MachXO
device
that
provides
the
following
functions:
• Local
bus
address
latching
and
chip
select
generation
for
Flash/NVRAM
• Control/Status
registers
• Watchdogs
• GPIO
controller
• Secondary
interrupt
controller
5.6.1 Ethernet
The
MPC8641D
has
four
on
‐
chip
enhanced
3
‐
speed
Ethernet
Controllers
(called
eTSECs).
These
incorporate
a
media
access
controller
(MAC)
that
supports
10/100/
1000BaseT,
and
half
‐
and
full
‐
duplex
operation.
The
eTSECs
support
several
TCP
offload
features
(including
checksum
generation
and
verification)
that
reduce
the
amount
of
software
interaction
required.
Jumbo
frames
are
also
supported.
The
SBC330
uses
two
of
these
controllers
to
provide
external
1000/100/10
Ethernet
interfaces.
eTSEC1
and
eTSEC3
are
used,
as
these
have
independent
connections
to
the
platform
bus.
The
controllers
are
connected
via
a
GMII
interface
to
Marvell
88E1111
PHYs.
The
PHYs
are
isolated
from
the
backplane
using
transformer
‐
coupled
magnetics.
The
PHYs
are
configured
at
power
‐
up
to
have
MDI
addresses
of
0x1
and
0x3,
corresponding
to
the
eTSEC
port
to
which
they
are
connected.
The
network
(MAC)
addresses
are
factory
configured.
Two
LEDs
indicating
link
‐
receive
are
provided
on
the
rear
side
at
the
front
edge
of
the
SBC330
board
to
allow
easy
monitoring
of
Ethernet
interface.
These
LEDs
should
flash
(yellow)
when
the
Ethernet
is
receiving
traffic.
5.6.2 Serial ports
The
DUART
module
in
the
MPC8641D
provides
COM1
and
COM2,
which
operate
as
debug
ports
for
the
two
processing
cores.
Each
of
the
two
UARTs
provides
16
‐
byte
FIFOs
and
is
software
‐
compatible
with
the
PC16450
and
PC16550D
UART
devices.
Hardware
flow
control
(RTS/CTS)
is
supported.
The
baud
rate
is
software
programmable
between
and
is
derived
from
the
MPX
bus
frequency
using
the
following
equation:
Baud
Rate
=
(1/16)
*
(MPX
Bus
Frequency/Divisor
Value)
