32 SBC330 3U VPX Single Board Computer
Publication No. SBC330-0HH/3
5.4.1 MPC8641D
The
MPC8641D
processor
has
two
8
‐
lane
high
‐
speed
I/O
ports,
termed
SERDES
(Serialiser/Deserialiser).
The
SERDES1
port
is
configured
as
a
x8
PCI
Express
link
and
is
connected
to
Port
0
of
the
PLX8518
16
‐
lane
PCIe
Switch.
This
port
is
normally
configured
as
the
system
PCIe
Root
Complex
at
power
up.
Although
it
would
be
possible
to
configure
this
port
as
a
PCIe
Endpoint
,
another
mechanism
is
used
to
allow
two
SBC330
boards
(i.e.
two
intelligent
Hosts
that
are
inherently
PCIe
Root
Complex
devices)
to
talk
to
each
other
via
their
SERDES1
ports.
The
SERDES2
port
is
configured
as
a
x8
PCI
Express
link
and
is
routed
to
directly
to
the
VPX
P1
and
P2
connectors.
This
port
is
normally
configured
as
the
system
PCIe
Root
Complex.
(This
port
can
be
configured
as
a
PCIe
Endpoint
by
fitting
the
FTS
test
jumper
to
the
SBC330RTM,
or
pulling
the
signal
on
pin
P2
G11
low.
This
technique
is
used
to
program
the
Flash
or
acquire
general
access
to
a
blank
SBC330
via
a
remote
SBC330
during
factory
bring
up.)
NOTE
Do not rely on non-persistent protection, as it may be subsequently altered by software. If further
protection is required, use the Persistent protection method.
5.4.2 PCI Express switch
The
SBC330
uses
a
PLX
PEX8518
PCI
Express
switch
to
connect
the
various
PCIe
devices
together.
This
device
is
a
16
‐
lane,
non
‐
blocking
PCIe
rev
1.1
switch
that
can
support
up
to
six
PCIe
ports.
The
device
also
supports
cut
‐
thru
mode
to
reduce
packet
latency.
On
the
SBC330,
the
PLX8518
is
set
up
to
operate
as
4
ports,
with
port
widths
of
x8,
x4,
x2,
and
x2.
The
switch
connects
to
the
processor
over
the
x8
port
for
maximum
bandwidth.
The
4
‐
lane
port
is
routed
to
the
P1
VPX
connector
for
external
IO.
One
2
‐
lane
port
is
routed
to
the
PEX8114
PCIe/PCI
Bridge
ultimately
to
connect
to
the
USB
interface.
The
other
2
‐
lane
port
is
connected
directly
to
the
Silicon
Image
Si3132
dual
SATA
Bridge,
where
only
1
of
the
2
lanes
is
required
to
handle
the
full
SATA
bandwidth.
In
this
way,
the
Switch
provides
connections
to
the
interfaces
at
the
bandwidths
required
to
allow
full
speed
access
to
the
different
I/O
interfaces
simultaneously.
Each
PCIe
port
of
the
PEX8518
appears
to
software
as
a
PCI
‐
to
‐
PCI
bridge,
with
its
own
PCI
‐
compatible
configuration
registers.
Each
port
is
accessed
on
the
internal
virtual
PCI
bus
using
a
device
number
equal
to
its
port
number.
The
port
configuration
of
the
switch
is
shown
in
Table
5
‐
7.
Table 5-7 PEX81518 Switch Ports
Port Number
Port Width
Lane Numbers
Connection
Type
0
x8
0 to 7
MPC8641D SerDes Port
1: 8-lane link
Upstream
1
x4
8 to 11
VPX connector external
4-lane link
Transparent
2
x2
12 only
SIL3132 SATA bridge
Transparent
3
x2
14 & 15
PEX8114 PCI-X bridge
Transparent
