Publication No. SBC330-0HH/3
FPGA Registers 69
6.17.4 Axis Timer control register
6.18 Test Register
This
32
‐
bit
read
‐
write
register
can
be
used
by
application
software
to
complement
the
two
16
‐
bit
scratch
registers.
Chip
Select
CS2
Offset
0x0038
LAD Bit
Reg Bit
R/W
Description
Reset Value
15
0
R/W
AXIS Timestamp Master/Slave
0 = Slave (do not drive selected clock source
to backplane)
1 = Master (drive selected on-board clock
source to backplane)
0x0
14
1
R/W
Timestamp reset
0 = Not in reset – timer can free run.
1 = Reset the counters at the next clock
0x0
13 to 8
2 to 7
R/W
6 bit Prescaler. Uses the 100 MHz or 133 MHz
local bus clock (if Master)
0x000000
7
8
R/W
Enable:
0 = Timer counters do not run
1 = Timer counters run
0x0
6
9
R/W
On-board clock source: 66. 6 MHz fixed
system clock
0 = Do not select 66.6 MHz on-board clock
1 = 66.6 MHz on-board clock selected
0x0
5
10
R/W
On-board clock source: Processor Local Clock
: 100, 133 MHz (DDR2 clock/2)
0 = Do not select Processor Local Bus clock
1 = Processor Local Bus clock selected
0x0
4
11
R/W
On-board clock source: 8 MHz fixed
0 = Do not select 8 MHz on-board clock
1 = 8 MHz on-board clock selected
0x0
3
12
R/W
On-board clock source: 250 KHz fixed
0 = Do not select 250 KHz on-board clock
1 = 250 KHz on-board clock selected
0x0
2
13
R/W
Not available in Rel 3 Firmware code
Chip
Select
CS2
Offset
0x00A8
LAD Bit
Reg Bit
R/W
Description
Reset Value
31 to 0
0 to 31
R/W
Scratch register (useful for local bus debug) 0x00000000
