GE SBC330 3U VPX, Справочник по аппаратуре

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Publication No. SBC330-0HH/3 FPGA Registers 53
6.5.1 GPIO input register
6.5.2 GPIO invert register
Chip Select CS2
Offset 0x0054
Reset value Depends on external signal conditions
LAD Bit Reg Bit R/W Description
15 0 R/W GPIO(0) input data
14 1 R/W GPIO(1) input data
13 2 R/W GPIO(2) input data
12 3 R/W GPIO(3) input data
11 4 R/W GPIO(4) input data
10 5 R/W GPIO(5) input data
9 6 R/W GPIO(6) input data
8 7 R/W GPIO(7) input data
Chip Select CS2
Offset 0x0058
Reset value 0x00
LAD Bit Reg Bit R/W Description
15 0 R/W GPIO(0) invert – write ‘1’ to invert the value into the GPIO
Input and Interrupt registers
14 1 R/W GPIO(1) invert – write ‘1’ to invert the value into the GPIO
Input and Interrupt registers
13 2 R/W GPIO(2) invert – write ‘1’ to invert the value into the GPIO
Input and Interrupt registers
12 3 R/W GPIO(3) invert – write ‘1’ to invert the value into the GPIO
Input and Interrupt registers
11 4 R/W GPIO(4) invert – write ‘1’ to invert the value into the GPIO
Input and Interrupt registers
10 5 R/W GPIO(5) invert – write ‘1’ to invert the value into the GPIO
Input and Interrupt registers
9 6 R/W GPIO(6) invert – write ‘1’ to invert the value into the GPIO
Input and Interrupt registers
8 7 R/W GPIO(7) invert – write ‘1’ to invert the value into the GPIO
Input and Interrupt registers