GE SBC330 3U VPX, Справочник по аппаратуре

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62 SBC330 3U VPX Single Board Computer Publication No. SBC330-0HH/3
6.11.2 CSR exclusive access semaphore register
This semaphore register works in the same way as the Hardware Exclusive Access
Semaphore Register described in Section 6.11 , without the complication of it
locking any other register. Reading this register sets it, and it must be written to
with a value of 0x0 to clear it. It is used for locking access to the FPGA registers,
and is part of maintaining exclusive access to shared resources between cores 0
and 1. At power ‐ up it is cleared to 0x0 such that it is available.
6.11.3 Test and Set (TAS) semaphore register
This Semaphore register works in the same way as the CSR Exclusive Semaphore
register.
Generally, its purpose is to support VxWorks Shared Memory Objects.
Core0….Core[n] of a multicore CPU uses this register to control access to an area
of shared memory, (normally volatile RAM). At power up it is cleared to 0x0 such
that it is available.
Chip Select CS2
Offset 0x007C
LAD Bit Reg Bit R/W Description Reset Value
15 0 R/W Read bit to take exclusive access.
Write 0x0 to clear 0x0
Chip Select CS2
Offset 0x0080
Reset value 0x0
LAD Bit Reg Bit R/W Description Reset Value
15 0 R/W Read Bit to take exclusive access :
Write 0x0 to Clear 0x0