GE SBC330 3U VPX, Справочник по аппаратуре

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Publication No. SBC330-0HH/3 FPGA Registers 47
6.2 Interrupt Registers
There are three registers associated with interrupts. SBC330 does not make use of
the wired ‐ OR interrupt inputs possible with the 8641D. All on ‐ board interrupts
are routed to the Interrupt Register in the FPGA and from this, any interrupting
source creates an interrupt to the 8641D on its IRQ8 signal input. On the SBC330
schematic, this is net CPLD_ALL_INT_OUT.
NOTE
Rev 3 boards connect a second line from the FPGA to IRQ11 of the Processor, which allows the
possibility of dual interrupt registers to be implemented in the FPGA code, 1 for each core. Later
software and firmware updates may make this available.
Interrupts are only passed to the processor if they are unmasked. At start ‐ up, the
FPGA code defaults to masking all interrupts. The on ‐ board interrupts can also be
set to be edge or level type. Edge interrupts are latched in the FPGA and need the
Interrupt register to be written to for them to be cleared. Level interrupts are not
latched and disappear if the interrupt source changes the level. All interrupts
signals are active ‐ low signals, but the Interrupt register uses a ‘1’ to represent an
active interrupt.
0x 0070 Hardware Exclusive Access Semaphore Read/write  
0x 0074 Core 0 Semaphore Read/write
 
0x 0078 Core 1 Semaphore Read/write  
0x 007C CSR Exclusive Access Semaphore Read/write
 
0x 0080 TAS Semaphore Read/write NA 
0x 0090 Watchdog 0 Control Read/write
 
0x 0094 Watchdog 0 Preset Read/write  
0x 0098 Watchdog 1 Control Read/write
 
0x 009C Watchdog 1 Preset Read/write  
0x 00A0 Watchdog 0 Interrupt Read/write
 
0x 00A4 Watchdog 1 Interrupt Read/write  
0x 00A8 Test Read/write
 
0x 00AC Configuration Resistors Read only  
0x 00B0 Axis FIFO A data Read Read only NA

0x 00B4 Axis FIFO A data Write Read/write NA 
0x 00B8 Axis FIFO A Control Read/write NA

0x 00BC Axis FIFO A Status Read only NA 
0x 00C0 Axis FIFO B data Read Read only NA

0x 00C4 Axis FIFO B data Write Read/write NA 
0x 00C8 Axis FIFO B Control Read/write NA

0x 00CC Axis FIFO B Status Read only NA 
Table 6-1 Register Offsets
Offset Register Name Type FPGA Rel 3 FPGA Rel 4