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CHAPTER 3: INSTALLATION DIRECT INPUT AND OUTPUT COMMUNICATIONS
C30 CONTROLLER SYSTEM – INSTRUCTION MANUAL 3-31
3
Figure 3-32: G.703 timing selection switch setting
Table 3-4: G.703 timing selections
3.4.4.3 G.703 octet timing
If octet timing is enabled (ON), this 8 kHz signal is asserted during the violation of bit 8 (LSB) necessary for connecting to
higher order systems. When C30s are connected back-to-back, octet timing is disabled (OFF).
3.4.4.4 G.703 timing modes
There are two timing modes for the G.703 module: internal timing mode and loop timing mode (default).
•
Internal Timing Mode — The system clock is generated internally. Therefore, set the G.703 timing selection to internal
timing mode for back-to-back (UR-to-UR) connections. For back-to-back connections, set octet timing (S1 = OFF) and
timing mode to internal timing (S5 = ON and S6 = OFF).
• Loop Timing Mode — The system clock is derived from the received line signal. Therefore, set the G.703 timing
selection to loop timing mode for connections to higher order systems. For connection to a higher order system (UR-
to-multiplexer, factory defaults), set to octet timing (S1 = ON) and set timing mode to loop timing (S5 = OFF and S6 =
OFF).
The switch settings for the internal and loop timing modes are shown.
Switches Function
S1 OFF → octet timing disabled
ON → octet timing 8 kHz
S5 and S6 S5 = OFF and S6 = OFF
→
loop timing mode
S5 = ON and S6 = OFF → internal timing mode
S5 = OFF and S6 = ON
→
minimum remote loopback mode
S5 = ON and S6 = ON → dual loopback mode