Fujitsu FR Family FR60 Lite, Руководство пользователя

Страница: 546 / 1038

530
Chapter 31 External Bus
2.External Bus Interface Registers
Table 2-27 lists the settings for burst write.
For connecting FCRAM, be sure to set the bit to 1.
FCRAM supports neither burst read nor single write mode.
[BIt 26] BANK (BANK type select): Bank number setting
Set this bit to the number of banks of SDRAM to be connected.
Table 2-28 lists the settings for bank number.
[Bits 25 - 24] ABS1, ABS0 (Active Bank Select): Setting of active bank number
Set these bits to the maximum number of banks to be made active simultaneously.
Table 2-29 lists the settings for the number of active banks.
2.5 Memory setting register (MCRB for FCRAM auto - precharge ON mode)
This section describes the memory setting register (MCRB for FCRAM auto - precharge ON
mode).
■
Structure of the Memory Setting Register (MCRB for FCRAM auto - precharge ON mode)
Settings for Memory configuration register (MCRB: Memory Configuration Register for extend type - B for FCRAM
auto - precharge ON mode) is used to make various settings for FCRAM connected to the chip select area.
Figure 2-5 shows the bit configuration of the memory setting register (MCRB for FCRAM auto - precharge ON
mode).
Table 2-18 Settings for burst write
WBST Settings for burst write
0 Single write
1 Burst write
Table 2-19 settings for bank number
BANK Settings for bank number
0 2 banks
1 4 banks
Table 2-20 Settings for the number of active banks
ABS1 ABS0 Number of active banks
0 0 1 bank
0 1 2 banks
1 0 3 banks
1 1 4 banks