110
Chapter 4 CPU Architecture
8.Word Alignment
8. Word Alignment
Since instructions and data are accessed by byte, allocated addresses vary by instruction length or
data width.
■
Program Access
FR60 program is required to be allocated in addresses multiplied by 2.
PC's bit0 is cleared for instruction execution upon the PC update.
(PC bit 0 may be set when odd address is specified for branching address, however, it is invalid. Since the
instruction is required to be allocated in addresses multiplied by 2, there is no odd address exception.)
■
Data Access
FR60 provides the following alignment for addresses depending on data width when executing data
access.
•
Word access
: Address is multiplied by 4. (Lowest order 2 bits are mandatorily 00.)
•
Half-word access : Address is multiplied by 2. (Lowest order bit is mandatorily 0.)
•
Byte access:
: Address is multiplied by 1.
Upon the word and half-word data accesses, some bits mandatorily become 0 for computing results
of effective address. For example, in the case of addressing mode of @(R13, Ri), register value
before addition is used as is (even if lowest order bit is 1), and lower bits of addition results are
masked. Register values before computing are not masked.
[Example] LD @(R13, R2), R0
R13
R2
00002222
00000003
Addition results
Address pin
00002225
H
00002224
H
Lower 2 bits are
mandatorily masked.
+)
Содержание FR Family FR60 Lite
Страница 2: ...FUJITSU LIMITED ...
Страница 3: ...FR60 32 BIT MICROCONTROLLER MB91460 Series User s Manual ...
Страница 15: ...xi ...
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Страница 38: ...22 Chapter 2 MB91460 Rev A Rev B Overview 4 Block Diagram ...
Страница 128: ...112 Chapter 4 CPU Architecture 9 Addressing ...
Страница 153: ...137 Chapter 8 Device State Transition 3 State Transition Diagram ...
Страница 154: ...138 Chapter 8 Device State Transition 3 State Transition Diagram ...
Страница 169: ...153 Chapter 9 Reset 10 Caution ...
Страница 170: ...154 Chapter 9 Reset 10 Caution ...
Страница 180: ...164 Chapter 10 Standby 7 Q A ...
Страница 182: ...166 Chapter 10 Standby 8 Caution ...
Страница 199: ...183 Chapter 12 Instruction Cache 2 Main body structure Figure 2 3 I Cache Address Map ...
Страница 200: ...184 Chapter 12 Instruction Cache 2 Main body structure Figure 2 4 I Cacheable Area ...
Страница 222: ...206 Chapter 13 Clock Control 8 Caution ...
Страница 232: ...216 Chapter 14 PLL Interface 7 Caution ...
Страница 236: ...220 Chapter 15 CAN Clock Prescaler 3 Registers ...
Страница 288: ...272 Chapter 19 Timebase Timer 8 Caution ...
Страница 314: ...298 Chapter 22 Main Oscillation Stabilisation Timer 8 Caution ...
Страница 326: ...310 Chapter 23 Sub Oscillation Stabilisation Timer 8 Caution ...
Страница 348: ...332 Chapter 25 External Interrupt 8 Caution ...
Страница 398: ...382 Chapter 26 DMA Controller 6 DMA External Interface ...
Страница 402: ...386 Chapter 27 Delayed Interrupt 8 Caution ...
Страница 412: ...396 Chapter 28 Bit Search 8 Caution ...
Страница 521: ...505 Chapter 30 I O Ports 3 Port Register Settings ...
Страница 522: ...506 Chapter 30 I O Ports 3 Port Register Settings ...
Страница 549: ...533 Chapter 31 External Bus 2 External Bus Interface Registers is set to the high impedance state ...
Страница 574: ...558 Chapter 31 External Bus 4 Endian and Bus Access Byte Access ...
Страница 628: ...612 Chapter 31 External Bus 13 Notes on Using the External Bus Interface ...
Страница 706: ...690 Chapter 33 I2C Controller 4 Programming Flow Charts ...
Страница 748: ...732 Chapter 34 CAN Controller 4 CAN Application ...
Страница 762: ...746 Chapter 35 Free Run Timer 8 Caution ...
Страница 790: ...774 Chapter 37 Output Compare 8 Caution ...
Страница 838: ...822 Chapter 39 Programmable Pulse Generator 8 Caution ...
Страница 850: ...834 Chapter 40 Pulse Frequency Modulator 4 PFM Operation and Setting ...
Страница 886: ...870 Chapter 42 Sound Generator 3 Registers ...
Страница 900: ...884 Chapter 43 Stepper Motor Controller 4 Caution ...
Страница 939: ...923 Chapter 47 LCD Controller 3 Configuration Figure 3 2 Register List ...
Страница 943: ...927 Chapter 47 LCD Controller 4 Registers Correspondence between VRAM and Common Segment Pins ...
Страница 964: ...948 Chapter 48 Clock Monitor 8 Caution ...
Страница 994: ...978 Chapter 51 Low Voltage Reset Interrupt 3 Registers ...
Страница 998: ...982 Chapter 52 Regulator Control 3 Registers ...
Страница 1008: ...992 Chapter 53 Fixed Mode Reset Vector BOOT ROM 5 Bootloader Update Strategy ...
Страница 1024: ...1008 Chapter 54 Flash Memory 8 Caution ...
Страница 1032: ...1016 Chapter 55 Flash Security 4 Register ...
Страница 1034: ...1018 Chapter 56 Electrical Specification ...
Страница 1035: ...FR60 MB91460 Series Hardware Manual European Microcontroller Design Centre Author MBo ...
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