712
Chapter 34 CAN Controller
2.Register Description
(Note)
When 11-bit (“standard”) Identifiers are used for a Message Object, the identifiers of received Data
Frames are written into bits ID28 to ID18. For acceptance filtering, only these bits together with mask
bits Msk28 to Msk18 are considered.
The Arbitration Registers ID28-0, Xtd, and Dir are used to define the identifier and type of outgoing messages
and are used (together with the mask registers Msk28-0, MXtd, and MDir) for acceptance filtering of incoming
messages. A received message is stored into the valid Message Object with matching identifier and Direction=
receive (Data Frame) or Direction= transmit(Remote Frame). Extended frames can be stored only in Message
Objects with Xtd = 1, standard frames in Message Objects with Xtd = 0. If a received message (Data Frame
or Remote Frame) matches with more than one valid Message Object, it is stored into that with the lowest
message number. For details see
4.5 “Acceptance Filtering of Received Messages” on page 726.
(Note)
This bit is used to concatenate two ore more Message Objects (up to 32) to build a FIFO Buffer. For
single Message Objects (not belonging to a FIFO Buffer) this bit must always be set to 1. For
details on the concatenation of Message Objects see chapter
4.13 “Configuration of a FIFO Buffer”
on page 728.
1
The 29-bit (“extended”) Identifier will be used for this Message Object.
MXtd
Mask Extended Identifier
0
The extended identifier bit (IDE) has no effect on the acceptance filtering
1
The extended identifier bit (IDE) is used for acceptance filtering.
Dir
Message Direction
0
Direction = receive: On TxRqst, a Remote Frame with the identifier of this Message Object is
transmitted. On reception of a Data Frame with matching identifier, that message is stored in
this Message Object.
1
Direction = transmit: On TxRqst, the respective Message Object is transmitted as a Data
Frame. On reception of a Remote Frame with matching identifier, the TxRqst bit of this Mes-
sage Object is set (if RmtEn = 1).
MDir
Mask Message Direction
0
The message direction bit (Dir) has no effect on the acceptance filtering.
1
The message direction bit (Dir) is used for acceptance filtering.
EoB
End of Buffer
0
Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO
Buffer.
1
Single Message Object or last Message Object of a FIFO Buffer.
NewDat
New Data
0
No new data has been written into the data portion of this Message Object by the Message
Handler since last time this flag was cleared by the CPU.
1
The Message Handler or the CPU has written new data into the data portion of this Message
Object.
Содержание FR Family FR60 Lite
Страница 2: ...FUJITSU LIMITED ...
Страница 3: ...FR60 32 BIT MICROCONTROLLER MB91460 Series User s Manual ...
Страница 15: ...xi ...
Страница 16: ...xii ...
Страница 38: ...22 Chapter 2 MB91460 Rev A Rev B Overview 4 Block Diagram ...
Страница 128: ...112 Chapter 4 CPU Architecture 9 Addressing ...
Страница 153: ...137 Chapter 8 Device State Transition 3 State Transition Diagram ...
Страница 154: ...138 Chapter 8 Device State Transition 3 State Transition Diagram ...
Страница 169: ...153 Chapter 9 Reset 10 Caution ...
Страница 170: ...154 Chapter 9 Reset 10 Caution ...
Страница 180: ...164 Chapter 10 Standby 7 Q A ...
Страница 182: ...166 Chapter 10 Standby 8 Caution ...
Страница 199: ...183 Chapter 12 Instruction Cache 2 Main body structure Figure 2 3 I Cache Address Map ...
Страница 200: ...184 Chapter 12 Instruction Cache 2 Main body structure Figure 2 4 I Cacheable Area ...
Страница 222: ...206 Chapter 13 Clock Control 8 Caution ...
Страница 232: ...216 Chapter 14 PLL Interface 7 Caution ...
Страница 236: ...220 Chapter 15 CAN Clock Prescaler 3 Registers ...
Страница 288: ...272 Chapter 19 Timebase Timer 8 Caution ...
Страница 314: ...298 Chapter 22 Main Oscillation Stabilisation Timer 8 Caution ...
Страница 326: ...310 Chapter 23 Sub Oscillation Stabilisation Timer 8 Caution ...
Страница 348: ...332 Chapter 25 External Interrupt 8 Caution ...
Страница 398: ...382 Chapter 26 DMA Controller 6 DMA External Interface ...
Страница 402: ...386 Chapter 27 Delayed Interrupt 8 Caution ...
Страница 412: ...396 Chapter 28 Bit Search 8 Caution ...
Страница 521: ...505 Chapter 30 I O Ports 3 Port Register Settings ...
Страница 522: ...506 Chapter 30 I O Ports 3 Port Register Settings ...
Страница 549: ...533 Chapter 31 External Bus 2 External Bus Interface Registers is set to the high impedance state ...
Страница 574: ...558 Chapter 31 External Bus 4 Endian and Bus Access Byte Access ...
Страница 628: ...612 Chapter 31 External Bus 13 Notes on Using the External Bus Interface ...
Страница 706: ...690 Chapter 33 I2C Controller 4 Programming Flow Charts ...
Страница 748: ...732 Chapter 34 CAN Controller 4 CAN Application ...
Страница 762: ...746 Chapter 35 Free Run Timer 8 Caution ...
Страница 790: ...774 Chapter 37 Output Compare 8 Caution ...
Страница 838: ...822 Chapter 39 Programmable Pulse Generator 8 Caution ...
Страница 850: ...834 Chapter 40 Pulse Frequency Modulator 4 PFM Operation and Setting ...
Страница 886: ...870 Chapter 42 Sound Generator 3 Registers ...
Страница 900: ...884 Chapter 43 Stepper Motor Controller 4 Caution ...
Страница 939: ...923 Chapter 47 LCD Controller 3 Configuration Figure 3 2 Register List ...
Страница 943: ...927 Chapter 47 LCD Controller 4 Registers Correspondence between VRAM and Common Segment Pins ...
Страница 964: ...948 Chapter 48 Clock Monitor 8 Caution ...
Страница 994: ...978 Chapter 51 Low Voltage Reset Interrupt 3 Registers ...
Страница 998: ...982 Chapter 52 Regulator Control 3 Registers ...
Страница 1008: ...992 Chapter 53 Fixed Mode Reset Vector BOOT ROM 5 Bootloader Update Strategy ...
Страница 1024: ...1008 Chapter 54 Flash Memory 8 Caution ...
Страница 1032: ...1016 Chapter 55 Flash Security 4 Register ...
Страница 1034: ...1018 Chapter 56 Electrical Specification ...
Страница 1035: ...FR60 MB91460 Series Hardware Manual European Microcontroller Design Centre Author MBo ...
Страница 1036: ......
Страница 1038: ......