16
Chapter 2 MB91460 Rev.A/Rev.B Overview
2.Features
• LIN-USART (LIN=Local Interconnect Network) : 16 channels
•
Full-duplex double buffer system (4 ch with 16 byte RX/TX FIFO buffer each)
•
With parity/without parity selectable
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1 or 2 stop bits selectable
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7 or 8 bits data length selectable
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NRZ type transfer format
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Asynchronous /synchronous communications selectable
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Master-slave communication function (multiprocessor mode)
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Dedicated baud rate prescaler is embedded in each channel
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External clock is able to use as transfer clock
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Parity error, frame error, and overrun error detecting functions
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SPI compatible
•
LIN master and slave
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LIN USART 0/8 and ICU 0 co-operate (for LIN sync field in slave mode)
•
LIN USART 1/9 and ICU 1 co-operate (for LIN sync field in slave mode)
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LIN USART 2/10 and ICU 2 co-operate (for LIN sync field in slave mode)
•
LIN USART 3/11 and ICU 3 co-operate (for LIN sync field in slave mode)
•
LIN USART 4/12 and ICU 4 co-operate (for LIN sync field in slave mode)
•
LIN USART 5/13 and ICU 5 co-operate (for LIN sync field in slave mode)
•
LIN USART 6/14 and ICU 6 co-operate (for LIN sync field in slave mode)
•
LIN USART 7/15 and ICU 7 co-operate (for LIN sync field in slave mode)
• CAN : 6 channels
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Supports CAN protocol version 2.0 part A and B
•
Bit rates up to 1 Mbit/s
•
Up to 128 message objects
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Each message object has its own identifier mask
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Programmable FIFO mode (cocatenation of message objects)
•
Maskable interrupt
•
Disabled Automatic Retransmission mode for Time Triggered CAN applications
•
Programmable loop-back mode for self-test operation
• I
2
C (400k fast mode) : 4 channels
•
Master or slave transmission
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Arbitration function
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Clock synchronization function
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Slave address and general call address detect function
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Transfer direction detect function
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Start condition repeat generation and detection function
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Bus error detect function
•
Compatible to I2C standard and fast mode specification (operation up to 400 kHz, 10 bit addressing)
•
Includes clock divider functionality
•
SCL and SDA lines include optional noise filter. The noise filter allows the suppression of spikes in
Содержание FR Family FR60 Lite
Страница 2: ...FUJITSU LIMITED ...
Страница 3: ...FR60 32 BIT MICROCONTROLLER MB91460 Series User s Manual ...
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Страница 38: ...22 Chapter 2 MB91460 Rev A Rev B Overview 4 Block Diagram ...
Страница 128: ...112 Chapter 4 CPU Architecture 9 Addressing ...
Страница 153: ...137 Chapter 8 Device State Transition 3 State Transition Diagram ...
Страница 154: ...138 Chapter 8 Device State Transition 3 State Transition Diagram ...
Страница 169: ...153 Chapter 9 Reset 10 Caution ...
Страница 170: ...154 Chapter 9 Reset 10 Caution ...
Страница 180: ...164 Chapter 10 Standby 7 Q A ...
Страница 182: ...166 Chapter 10 Standby 8 Caution ...
Страница 199: ...183 Chapter 12 Instruction Cache 2 Main body structure Figure 2 3 I Cache Address Map ...
Страница 200: ...184 Chapter 12 Instruction Cache 2 Main body structure Figure 2 4 I Cacheable Area ...
Страница 222: ...206 Chapter 13 Clock Control 8 Caution ...
Страница 232: ...216 Chapter 14 PLL Interface 7 Caution ...
Страница 236: ...220 Chapter 15 CAN Clock Prescaler 3 Registers ...
Страница 288: ...272 Chapter 19 Timebase Timer 8 Caution ...
Страница 314: ...298 Chapter 22 Main Oscillation Stabilisation Timer 8 Caution ...
Страница 326: ...310 Chapter 23 Sub Oscillation Stabilisation Timer 8 Caution ...
Страница 348: ...332 Chapter 25 External Interrupt 8 Caution ...
Страница 398: ...382 Chapter 26 DMA Controller 6 DMA External Interface ...
Страница 402: ...386 Chapter 27 Delayed Interrupt 8 Caution ...
Страница 412: ...396 Chapter 28 Bit Search 8 Caution ...
Страница 521: ...505 Chapter 30 I O Ports 3 Port Register Settings ...
Страница 522: ...506 Chapter 30 I O Ports 3 Port Register Settings ...
Страница 549: ...533 Chapter 31 External Bus 2 External Bus Interface Registers is set to the high impedance state ...
Страница 574: ...558 Chapter 31 External Bus 4 Endian and Bus Access Byte Access ...
Страница 628: ...612 Chapter 31 External Bus 13 Notes on Using the External Bus Interface ...
Страница 706: ...690 Chapter 33 I2C Controller 4 Programming Flow Charts ...
Страница 748: ...732 Chapter 34 CAN Controller 4 CAN Application ...
Страница 762: ...746 Chapter 35 Free Run Timer 8 Caution ...
Страница 790: ...774 Chapter 37 Output Compare 8 Caution ...
Страница 838: ...822 Chapter 39 Programmable Pulse Generator 8 Caution ...
Страница 850: ...834 Chapter 40 Pulse Frequency Modulator 4 PFM Operation and Setting ...
Страница 886: ...870 Chapter 42 Sound Generator 3 Registers ...
Страница 900: ...884 Chapter 43 Stepper Motor Controller 4 Caution ...
Страница 939: ...923 Chapter 47 LCD Controller 3 Configuration Figure 3 2 Register List ...
Страница 943: ...927 Chapter 47 LCD Controller 4 Registers Correspondence between VRAM and Common Segment Pins ...
Страница 964: ...948 Chapter 48 Clock Monitor 8 Caution ...
Страница 994: ...978 Chapter 51 Low Voltage Reset Interrupt 3 Registers ...
Страница 998: ...982 Chapter 52 Regulator Control 3 Registers ...
Страница 1008: ...992 Chapter 53 Fixed Mode Reset Vector BOOT ROM 5 Bootloader Update Strategy ...
Страница 1024: ...1008 Chapter 54 Flash Memory 8 Caution ...
Страница 1032: ...1016 Chapter 55 Flash Security 4 Register ...
Страница 1034: ...1018 Chapter 56 Electrical Specification ...
Страница 1035: ...FR60 MB91460 Series Hardware Manual European Microcontroller Design Centre Author MBo ...
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