Fujitsu FR Family FR60 Lite, Руководство пользователя

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Chapter 31 External Bus
2.External Bus Interface Registers
[Bits 3] W03 (WR0-WR3, WRn Output Timing Selection)
The WR0-WR3, WRn output timing setting selects whether to use write strobe output as an asynchronous
strobe or synchronous write enable. The asynchronous strobe setting corresponds to normal memory/IO.
The synchronous enable setting corresponds to clock-synchronized memory/IO (such as the memory in an
ASIC).
If synchronous write enable (W03 bit of AWR is 1) is used, operations are as follows:
• The timing of synchronous write enable output assumes that the output is captured by the rising edge of
MCLK output of an external memory access clock. This timing is different from the asynchronous strobe
output timing.
• The WR0-WR3 and WRn terminal output asserts synchronous write enable output at the timing at which AS
pin output is asserted. For a write to an external bus, the synchronous write enable output is L. For a read
from an external bus, the synchronous write enable output is H.
• Write data is output from the external data output pin in the clock cycle following the cycle in which
synchronous write enable output is asserted.
If write data cannot be output because the internal bus is
temporarily unavailable, assertion of synchronous write enable output may be extended until write data can be
output.
• Read strobe output (RD) functions as an asynchronous read strobe regardless of the setting of the WR0-WR3
and WRn output timing. Use it as is for controlling the data I/O direction.
If synchronous write enable output is used, the following restrictions apply:
• Do not make the following additional wait settings:
• CSn -> RD/WRn setup (Always set 0 for the W01 bit of AWR)
• First wait cycle setting (Always set 0000
B
for the W15-W12 bits of AWR)
• Do not make the following access type settings (TYPE3-0 bits in the ACR register (bits 3-0))
• Address/data multiplex bus setting (Always set 0 for the TYPE2 bit of ACR)
• Setting to use WR0-WR3 as a strobe (Always set 0 for the TYPE1 bit of ACR)
• RDY input enable setting (Always set 0 for the TYPE0 bit of ACR)
• For synchronous write enable output, always set 1(00
B
for bits BST1-0 bits of ACR) as the burst length.
W03 WR0-WR3, WRn output timing selection
0 MCLK synchronous write enable output (valid from AS=L)
1 Asynchronous write strobe output (normal operation)