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CHAPTER 20 LIN-UART
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Explanation of the different blocks
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Reload Counter
The reload counter is a 15-bit reload counter that functions as the dedicated baud rate generator. It can
select external clock or internal clock for the transmitting and receiving clocks. The reload counter has a
15-bit register for the reload value. The actual count of the transmission reload counter can be read via the
BGRn0/n1.
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Reception Control Circuit
The reception control circuit consists of a received bit counter, start bit detection circuit, and received
parity counter. The received bit counter counts reception data bits. When reception of one data item for the
specified data length is completed, the received bit counter sets the reception data register full flag. In this
case, if the reception interrupt is enabled, the reception interrupt request is generated. The start bit detection
circuit detects start bits from the serial input signal and sends a signal to the reload counter to synchronize it
to the falling edge of these start bits. The received parity counter calculates the parity of the reception data.
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Reception Shift Register
The reception shift register fetches reception data input from the SINn pin, shifting the data bit by bit.
When reception is completed, the reception shift register transfers receive data to the RDR register.
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Reception Data Register (RDR)
This register retains reception data. Serial input data is converted and stored in this register.
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Transmission Control Circuit
The transmission control circuit consists of a transmission bit counter, transmission start circuit, and
transmission parity counter. The transmission bit counter counts transmission data bits. When the
transmission of one data item of the specified data length is completed, the transmission bit counter sets the
transmission data register full flag. In this case, if the transmission interrupt is enabled, the transmission
interrupt request is generated. The transmission start circuit starts transmission when data is written to TDR
register. The transmission parity counter generates a parity bit for data to be transmitted if parity is enabled.
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Transmission Shift Register
The transmission shift register transfers data written to the TDR register to itself and outputs the data to the
SOTn pin, shifting the data bit by bit.
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Transmission Data Register (TDR)
This register sets transmission data. Data written to this register is converted to serial data and outputted.
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Error Detection Circuit
The error detection circuit checks if there was any error during the last reception. If an error has occurred it
sets the corresponding error flags.
Содержание F2MCTM-16LX
Страница 2: ......
Страница 3: ...FUJITSU LIMITED F2MCTM 16LX 16 BIT MICROCONTROLLER MB90360 Series HARDWARE MANUAL ...
Страница 4: ......
Страница 42: ...26 CHAPTER 1 OVERVIEW ...
Страница 66: ...50 CHAPTER 2 CPU MOV ILM imm8 The instruction is executed normally but the prefix affects the next instruction ...
Страница 70: ...54 CHAPTER 2 CPU ...
Страница 134: ...118 CHAPTER 6 CLOCK SUPERVISOR ...
Страница 176: ...160 CHAPTER 8 LOW POWER CONSUMPTION MODE ...
Страница 194: ...178 CHAPTER 10 I O PORTS ...
Страница 252: ...236 CHAPTER 13 16 Bit I O TIMER ...
Страница 282: ...266 CHAPTER 14 16 BIT RELOAD TIMER ...
Страница 295: ...279 CHAPTER 15 WATCH TIMER ORG 00FFDCH Reset vector set DSL START DB 00H Set to single chip mode VECT ENDS END START ...
Страница 296: ...280 CHAPTER 15 WATCH TIMER ...
Страница 386: ...370 CHAPTER 18 8 10 BIT A D CONVERTER ...
Страница 426: ...410 CHAPTER 20 LIN UART Figure 20 5 2 ORE Flag Set Timing RDRF ORE Reception data ...
Страница 540: ...524 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ...
Страница 568: ...552 CHAPTER 24 512K BIT FLASH MEMORY ...
Страница 633: ...617 APPENDIX B Instructions Table B 9 3 Bit Operation Instruction Map first byte 6CH ...
Страница 634: ...618 APPENDIX Table B 9 4 Character String Operation Instruction Map first byte 6EH ...
Страница 635: ...619 APPENDIX B Instructions Table B 9 5 2 byte Instruction Map first byte 6FH MUL MULW DIVU A A A ...
Страница 637: ...621 APPENDIX B Instructions Table B 9 7 ea Instruction 2 first byte 71H ...
Страница 638: ...622 APPENDIX Table B 9 8 ea Instruction 3 first byte 72H ...
Страница 639: ...623 APPENDIX B Instructions Table B 9 9 ea Instruction 4 first byte 73H ...
Страница 640: ...624 APPENDIX Table B 9 10 ea Instruction 5 first byte 74H ...
Страница 641: ...625 APPENDIX B Instructions Table B 9 11 ea Instruction 6 first byte 75H ...
Страница 642: ...626 APPENDIX Table B 9 12 ea Instruction 7 first byte 76H ...
Страница 643: ...627 APPENDIX B Instructions Table B 9 13 ea Instruction 8 first byte 77H ...
Страница 644: ...628 APPENDIX Table B 9 14 ea Instruction 9 first byte 78H ...
Страница 645: ...629 APPENDIX B Instructions Table B 9 15 MOVEA RWi ea Instruction first byte 79H ...
Страница 646: ...630 APPENDIX Table B 9 16 MOV Ri ea Instruction first byte 7AH ...
Страница 647: ...631 APPENDIX B Instructions Table B 9 17 MOVW RWi ea Instruction first byte 7BH ...
Страница 648: ...632 APPENDIX Table B 9 18 MOV Ri ea Instruction first byte 7CH ...
Страница 649: ...633 APPENDIX B Instructions Table B 9 19 MOVW ea Rwi Instruction first byte 7DH ...
Страница 650: ...634 APPENDIX Table B 9 20 XCH Ri ea Instruction first byte 7EH ...
Страница 651: ...635 APPENDIX B Instructions Table B 9 21 XCHW RWi ea Instruction first byte 7FH ...
Страница 664: ...648 APPENDIX ...
Страница 665: ...649 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
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