Freescale Semiconductor
11-1
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Chapter 11
Static RAM (SRAM)
11.1
Introduction
This chapter describes the on-chip static RAM (SRAM) implementation, including general operations,
configuration, and initialization. It also provides information and examples showing how to minimize
power consumption when using the SRAM.
11.1.1
Overview
The SRAM module provides a general-purpose memory block that the ColdFire processor can access in a
single cycle. The location of the memory block can be specified to any 0-modulo-32K address. The
memory is ideal for storing critical code or data structures or for use as the system stack. Because the
SRAM module is physically connected to the processor's high-speed local bus, it can service
processor-initiated accesses or memory-referencing commands from the debug module.
The SRAM is dual-ported to provide DMAaccess. The SRAM is partitioned into two physical memory
arrays to allow simultaneous access to arrays by the processor core and another bus master. For more
information see
Chapter 10, “System Control Module (SCM)
”
11.1.2
Features
The major features includes:
•
One 32 Kbyte SRAM
•
Single-cycle access
•
Physically located on the processor's high-speed local bus
•
Memory location programmable on any 0-modulo-32 Kbyte address
•
Byte, word, and longword address capabilities
11.2
Memory Map/Register Description
The SRAM programming model shown in
includes a description of the SRAM base address
register (RAMBAR), SRAM initialization, and power management.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
