Force SYS68K/CPU-30 R4, Техническое справочное руководство

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Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual
Page 52
NOTE: The setup parameters of FGA-002 are stored in the SRAM
located in the lower half of the SRAM address space. If the optional
SRAM is enabled, the setup parameters of the optional SRAM will be
used.
3.7.3 Access Time
Selection of the
SRAM Area The access time of the SRAM area is software programmable in the
FGA-002 Gate Array. Four fixed access times are available: 2.0, 1.0, 0.5
and 0.25 microseconds.
3.7.4 Backup Power
for the SRAM
Area There are two sources for backup power. One from the VMEbus
+5VSTDBY line and the other one from a CR2032-type lithium battery
installed in the battery socket at location BAT 1.
Backup power from the 5VSTDBY line is enabled by
SW11-2. Backup power from the battery is enabled by SW11-1.
The SRAM memory, both the default SRAM (on-board) and the optional
SRAM (sockets J87 and J88) are powered by backup power circuitry.
This maintains the power supply for the SRAM memory to retain its non-
volatile storage.
Under normal operation the backup power circuitry connects the +5V
power supply to the SRAM memory. When the main +5V supply fails,
backup power may be supplied from one of two alternate sources. The
5VSTDBY line may be used to provide backup power under
power-fail conditions. The switchover from 5V to +5VSTDBY
is fully automatic; whichever voltage is higher will be available to the
SRAM memory.
As a second alternative, the backup power may be supplied by battery.
Should the +5V and/or +5VSTDBY supplies drop below approximately
+3.3 volts, the on-board battery will be used.
This is controlled for +5VSTDBY by switch SW11-2.
SW11-2 Description
OFF (default) Backup from +5VSTDBY for RTC and SRAM disabled
ON Backup from +5VSTDBY for RTC and SRAM enabled
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