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SYS68K/CPU-30 R4 Technical Reference Manual

Hardware Description

Page 83

Information transfers on the data bus are asynchronous and follow a
defined REQ/ACK handshake protocol. One byte of information may be
transferred with each handshake. An option is defined for synchronous
data transfer.

3.11.4.2 SCSIbus Signal

Termination

Each SCSIbus signal should be terminated at the physical start and the
physical end of the SCSIbus. Therefore, the CPU-30 R4 provides
circuitry for active termination.

Active termination can be controlled by switch SW7-3.

3.11.4.3 SCSIbus

Terminator
Power

The power for the terminator of any SCSI device will be provided from
the CPU board directly, or from the SCSIbus itself. If termination power
is not delivered from any other SCSI device, it is delivered from the CPU
board.

The TERMPWR (terminator power) supply from the CPU board is
protected by a self resetting fuse (1A max) and a diode in series, as
defined in the SCSI specification.

The on-board terminators will draw power from the SCSIbus
TERMPWR.

3.11.5 Summary of

the SCSIbus
Controller

Device

MB 87034

Access Address

FF80.3400

16

Port Width

Byte

Interrupt Request Level

Software Programmable

FGA-002 Interrupt Request Channel

Local IRQ #7

SW7-3

Description

OFF

Active SCSI termination on

ON

Active SCSI termination off

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Содержание SYS68K/CPU-30 R4

Страница 1: ...ll Rights Reserved This document shall not be duplicated nor its contents used for any purpose unless express permission has been granted Copyright by FORCE COMPUTERS SYS68K CPU 30 R4 Technical Refere...

Страница 2: ...4 2 1 3 Specifications 7 1 4 Ordering Information 9 1 5 History of Manual Publication 10 2 Installation 11 2 1 Introduction 11 2 1 1 Caution 11 2 1 2 Board Installation 12 2 2 Location Diagrams of the...

Страница 3: ...sor 32 3 2 1 Hardware Interface of the 68030 32 3 2 2 The Instruction Set 32 3 2 3 Vector Table of the 68030 33 3 3 The Floating Point Coprocessor FPCP 34 3 3 1 Features of the 68882 34 3 3 2 Interfac...

Страница 4: ...onal Boot PROM Socket J28 46 3 6 1 3 Programming the Boot PROM Devices 46 3 6 1 4 Programming Flash Devices 47 3 6 2 The Boot PROM Address Map 47 3 6 2 1 Address Map of the Default Boot PROM Socket J3...

Страница 5: ...f the PI T 68 3 10 2 Address Map of the PI T 1 Registers 69 3 10 3 I O Configuration of PI T 1 69 3 10 4 Rotary Switches at PI T 1 70 3 10 5 Floppy Disk Drive Control Lines at PI T 1 71 3 10 6 DMA Con...

Страница 6: ...1SCSIbus Configuration 82 3 11 4 2SCSIbus Signal Termination 83 3 11 4 3SCSIbus Terminator Power 83 3 11 5 Summary of the SCSIbus Controller 83 3 12 The Floppy Disk Controller 84 3 12 1 Features of th...

Страница 7: ...ABORT Function Switch 92 3 14 3 RUN LED 92 3 14 4 BM LED 93 3 14 5 Rotary Switches 93 3 14 6 Reserved Switches 93 3 15 The CPU Board Interrupt Structure 94 3 16 VMEbus Interface 95 3 17 VMEbus Master...

Страница 8: ...t 1 Situation 107 3 21 2 Slot 1 Status Register 108 3 21 3 Enabling the Arbiter 108 3 21 4 The SYSCLK Driver 109 3 21 5 VMEbus Timer 109 3 22 Exception Signals 110 3 22 1 The SYSFAIL Signal 110 3 22 2...

Страница 9: ...ET Switch 127 5 4 2 ABORT Switch 127 5 4 3 Control Switches Rotary Switches 127 5 4 4 Default Memory Usage of VMEPROM 130 5 4 5 Default ROM Usage of VMEPROM 130 6 Devices and Interrupts used by VMEPRO...

Страница 10: ...AL Perform Functional Test 144 8 9 MEM Set Data Bus Width of the VMEbus 144 8 10 SELFTEST Perform On board Selftest 145 8 11 Installing a New Hard Disk 146 9 Appendix to VMEPROM 149 9 1 Driver Install...

Страница 11: ...2 CONT Continue with Calling Routine 181 10 3 DI Disassembler 182 10 4 DRAMINIT Initialize DRAM 182 10 5 FERASE Erase Flash Memories 183 10 6 FPROG Program Flash Memories 184 10 7 GO Go to Subroutine...

Страница 12: ...1 Diagram of the CPU 30 R4 Top View 13 Figure 2 Diagram of the CPU 30 R4 Bottom View 14 Figure 3 Front Panel 19 Figure 4 The 48 bit 6 byte Ethernet address 88 Figure 5 Functional Block Diagram of the...

Страница 13: ...USCC 2 Register Address Map 62 Table 22 Ports 2 and 3 DUSCC 2 Common Register Address Map 62 Table 23 Switches Module Assignment for Serial Port Configuration 63 Table 24 PI T 1 Register Layout 69 Tab...

Страница 14: ...of the product the specifications the ordering information and the publication history of the manual Information concerning the installation default configuration initialization and connector pinouts...

Страница 15: ...se refer to Table 2 Ordering Information on page 9 for more detailed information The shared DRAM is accessible from the 68030 CPU the FGA 002 DMA controller and also from other VMEbus masters The CPU...

Страница 16: ...s Standard non privileged data program access Short supervisory access Short non privileged access Extended supervisory data program access Extended non privileged data program access Slave A32 D8 D16...

Страница 17: ...k to back reception with as little as 4 1 s inter packet gaptime AUI Ethernet available on the front panel via a standard 15 pin D Sub connector SCSI Interface Via MB87033 34 Full support for SCSI con...

Страница 18: ...ditional software allows the support of HDLC SDLC BISYNC etc Three ports available on the front panel via standard 9 pin D Sub connectors One port available on standard 3 row VMEbus P2 connector All c...

Страница 19: ...er included year month week day Built in quartz oscillator 12 hr 24 hr clock switch over Automatic leap year setting CMOS design provides low power consumption during power down mode On board battery...

Страница 20: ...3 row VME P2 connec tor and 1 via the optional 5 row VME P2 connector via FORCE hybrids Ethernet Interface Ethernet SRAM buffer AM7990 64 Kbyte Parallel I O interface optional Via 68230 PI T 20 lines...

Страница 21: ...versions 512 Kbyte Power requirements 5 V max 12 V max 12 V max typical 2 3A typical 0 4A typical 0 1A Operating temperature with forced air cooling Storage temperature Relative humidity non condensin...

Страница 22: ...25 MHz 8 Mbyte shared DRAM 4 Mbyte Flash 4 serial ports 32 bit VMEbus interface VMEPROM firmware Installation Guide CPU 30 TM Rev 4 Technical Reference Manual Set for the CPU 30 Rev 4 including a deta...

Страница 23: ...ical Reference Manual Table 3 History of Manual Edition No Description Date 1 First Print February 1996 2 Rotary switch description in the section VMEPROM has been corrected Ethernet address has been...

Страница 24: ...the board To ensure proper functioning of the product over its usual lifetime take the following precautions before handling the board Electrostatic discharge and incorrect board installation and unin...

Страница 25: ...on 2 3 Default Switch Settings 2 2 Location Diagrams of the SYS68K CPU 30 R4 Board A location diagram showing the important components on the top side of the CPU 30 R4 appears on the next page On the...

Страница 26: ...CSI 87034 FDC 37C65C PT1 PT2 DUS1 DUS2 J25 J26 Boot EPROM Optional Boot EPROM LANCE 7970 NVRAM Optional NVRAM Battery 7992 SIA Reset Switch Abort Switch Run LED BM LED SW3 SW4 Rotary Switches AUI Ethe...

Страница 27: ...Diagram of the CPU 30 R4 Bottom View SW12 SW8 SW6 SW7 SW5 SW13 SW11 1 2 3 4 OFF ON NOTE Pin 1 is always located near the diagonal line shown on each switch and the OFF side of the switch is also alwa...

Страница 28: ...ss to default Boot PROM is disabled SW5 2 OFF OFF Optional Boot PROM Pinout for Flash PROM ON Optional Boot PROM Pinout for EPROM SW5 3 OFF OFF Write to Boot PROM enabled ON Write to Boot PROM disable...

Страница 29: ...enabled ON VME_SYSFAIL output disabled SW8 3 OFF OFF VME_SYSRESET output enabled ON VME_SYSRESET output disabled SW8 4 OFF OFF VME_SYSRESET input enabled ON VME_SYSRESET input disabled SWITCH 11 SW11...

Страница 30: ...S 232 Hybrid FH 002 ON Serial channel 3 for RS 422 Hybrid FH 003 SW12 4 OFF OFF Serial channel 4 for RS 232 Hybrid FH 002 ON Serial channel 4 for RS 422 Hybrid FH 003 SWITCH 13 SW13 1 OFF OFF Timer IR...

Страница 31: ...panel devices are briefly described on the pages following the drawing Table 5 Front Panel Layout Device Function Name Switch Reset RESET Switch Abort ABORT LED RUN HALT RUN LED VME BM BM Rotary Switc...

Страница 32: ...Manual Installation Page 19 Figure 3 Front Panel RESET ABORT SYS68K CPU 30 R4 RUN BM 2 1 1 2 3 L Rotary Switches RESET and ABORT Keys Status LEDs 15 pin D Sub Connector 9 pin D Sub Connector 9 pin D...

Страница 33: ...s master BM LED is used to indicate VMEbus mastership of the CPU 30 R4 and in this case the LED turns green 2 4 3 Voltage Sensor The voltage sensor generates a power up reset if the voltage level is b...

Страница 34: ...the signal DSR is always read active by software The RS 232 interface on your current CPU 30 revision 4 x board is fully compatible to the RS 232 interface on the earlier CPU 30 revision 3 2 board Ho...

Страница 35: ...he FGA Boot debugger FGA Boot also provides a utility function to get the CPU board s Ethernet address 40 0x28 Get Ethernet Number The following table shows the pinout of the AUI Ethernet connector Ta...

Страница 36: ...ng switches control the SCSI termination NOTE TERMPWR is always supplied if termination power is supplied externally by a source other than the VME connector the active termination is still maintained...

Страница 37: ...9 PIT2 A4 SCSI DP FDC DIREC GND Port 1 10 GND GND FDC STEPX TxD Port 2 11 PIT2 A5 GND FDC WDATA RxD Port 2 12 GND GND FDC WGATE RTS Port 2 13 PIT2 A6 TERMPWR FDC TRK00 CTS Port 2 14 GND GND FDC WPROT...

Страница 38: ...F The different functions of the rotary switches are described in detail in the VMEPROM section of the SYS68K CPU 30 R4 Technical Reference Manual Correct Operation To test the correct operation of th...

Страница 39: ...SYS68K IOBP 1 Pin Assignment PIN No IOBP 1 P1 PIN No VMEbus P2 Row A Signal Mnemonic Row B Signal Mnemonic Row C Signal Mnemonic 32 1 DB 0 SCSI 31 2 DB 1 SCSI GND 30 3 DB 2 SCSI Drive Select 4 2 FDC 2...

Страница 40: ...ual Installation Page 27 3 30 RTS SER RXD SER 2 31 CTS SER GND TXD SER 1 32 GND SER DTR SER Table 10 SYS68K IOBP 1 Pin Assignment Continued PIN No IOBP 1 P1 PIN No VMEbus P2 Row A Signal Mnemonic Row...

Страница 41: ...Installation SYS68K CPU 30 R4 Technical Reference Manual Page 28...

Страница 42: ...rd up to 8 Mbyte System Flash an Ethernet Interface a single ended SCSI interface a Floppy interface four RS 232 serial I O channels up to 256 Kbyte SRAM and a Real Time Clock both with on board batte...

Страница 43: ...space n a N N 32 16 8 FBFF 000016 FBFF FFFF16 VME A16 short address space n a N N 32 16 8 FC00 000016 FCFE FFFF16 VME A24 standard address space n a N N 16 8 FCFF 000016 FCFF FFFF16 VME A16 short add...

Страница 44: ...FF16 SCSI Controller N N N 8 FF80 360016 FF80 37FF16 reserved n a n a n a n a FF80 380016 FF80 397F16 The Floppy Disk Controller N N N 8 FF80 397F16 FF80 39FF16 Slot 1 status register RO N N N 8 ro FF...

Страница 45: ...31 are also driven from the processor on write cycles and sensed on read cycles The size of the data transfer is defined by the SIZE A0 A1 output signals always driven from the CPU During asynchronous...

Страница 46: ...03816 03C16 Coprocessor Protocol Violation Format Error Uninitialized Interrupt 16 23 04016 05C16 Unassigned Reserved 24 25 26 27 28 29 30 31 06016 06416 06816 06C16 07016 07416 07816 07C16 Spurious I...

Страница 47: ...nd instruction address 67 bit arithmetic unit 67 bit barrel shifter 46 instructions with 35 arithmetic operations IEEE 754 compatible including all requirements and suggestions Full set of trigonometr...

Страница 48: ...ransfers are performed by the main processor at the request of the 68882 thus memory management bus errors address errors and bus arbitration function as if the 68882 instructions are executed by the...

Страница 49: ...or ID 001 Please note that the VMEPROM Assembler supports this function by default 3 3 5 Detection of the 68882 The SENSE pin of the FPCP is connected to PI T 1 This allows automatic detection whether...

Страница 50: ...n the FGA 002 Gate Array User s Manual 3 4 2 Shared DRAM The CPU board contains a Shared dynamic RAM area with a capacity of 4 8 16 or 32 Mbytes The Shared RAM area is optimized for fast accesses from...

Страница 51: ...epends on memory size The Dual Banks architecture implements an interleaved organized DRAM four consecutive bytes located in bank A the next four consecutive bytes located in bank B The Single Bank ar...

Страница 52: ...he VMEbus transaction overhead A programmable bit within the FGA 002 may be used to disable the early bus release option With early release disabled the FGA 002 retains local bus mastership until the...

Страница 53: ...rammable via FGA 002 That is the address range that other VMEbus masters must use in order to access the Shared RAM on the CPU board This is not necessarily the same address range used by the CPU for...

Страница 54: ...1 1 burst transfer Overall the total cache line burst fill operation requires 8 clock cycles to transfer 16 bytes providing a memory bandwidth of over 50 Mbytes second Not all CPU accesses are burst...

Страница 55: ...SP and IPC loaded at address 0000 000016 and 0000 000416 respectively 0000 000016 in System Flash Memory Initial Interrupt Stack Pointer 0000 000416 in System Flash Memory Initial Program Counter 3 5...

Страница 56: ...ALSO For further details please refer to the data sheets for Flash devices in Section 4 Circuit Schematics and Data Sheets on page 115 This communication sequence has to be performed on every byte pa...

Страница 57: ...dress map for the usable device types 3 5 7 Summary of the PROM Area Not Allowed Access with Function Code 111 Usable Data Bits D00 D31 Supported Port Size read Long Word Byte Supported Port Size writ...

Страница 58: ...ers After bootup the Boot PROM will be accessible at address FFE0 000016 The start address of the Boot PROM is fixed and cannot be changed 3 6 1 The Boot PROM Sockets The Boot PROM area is located in...

Страница 59: ...devices must be used which is defined by the manufacturer of the device SEE ALSO For further details please refer to the data sheets in Section 4 Circuit Schematics and Data Sheets on page 115 The pro...

Страница 60: ...d as an output 3 6 2 The Boot PROM Address Map 3 6 2 1 Address Map of the Default Boot PROM Socket J36 Boot PROM access to default Boot PROM and optional Boot PROM Boot PROM selection switch SW5 1 in...

Страница 61: ...FFE8 FFFF16 64K 8 28C010 FFE8 000016 FFE9 FFFF16 128K 8 28F512A FFE8 000016 FFE8 FFFF16 64K 8 28F010A FFE8 000016 FFE9 FFFF16 128K 8 28F020A FFE8 000016 FFEB FFFF16 256K 8 27C010 EPROM OTP FFE8 00001...

Страница 62: ...Description Page 49 3 6 3 Summary of the Boot PROM Area Not Allowed Access with Function Code 111 Supported Port Size Byte Maximum Capacity 1 Mbyte Default Access Time 200 ns Access Address FFE0 0000...

Страница 63: ...y at sockets J86 J87 and J88 allows the user to retain data when the power supply is switched off A backup provides the current for the SRAM standby mode 3 7 1 Memory Organization SRAM The local SRAM...

Страница 64: ...ition The package type must be either 28 pin DIL or 32 pin DIL The following DIL device types are supported by the J88 socket position CAUTION A device can only be assembled in either socket J87 or J8...

Страница 65: ...abled by SW11 1 The SRAM memory both the default SRAM on board and the optional SRAM sockets J87 and J88 are powered by backup power circuitry This maintains the power supply for the SRAM memory to re...

Страница 66: ...Code 111 Supported Port Size Byte Default Access Time 100ns Access Address FFC0 000016 FFCF FFFF16 Capacity of Default SRAM 32 Kbytes Maximum Capacity of Optional SRAM 512 Kbytes SW11 1 SW11 3 Defaul...

Страница 67: ...date and time registers SEE ALSO For further details please refer to the RTC 72423 data sheet in Section 4 Circuit Schematics and Data Sheets on page 115 Table 16 RTC Register Layout Default I O Base...

Страница 68: ...0 rtc sec1reg 0x0f sy _smin unsigned char rtc min10reg 0x07 10 rtc min1reg 0x0f sy _shrs unsigned char rtc hou10reg 0x03 10 rtc hou1reg 0x0f sy _syrs 0 unsigned char rtc yr10reg 0x0f 10 rtc yr1reg 0x0...

Страница 69: ...e used to provide backup power under power fail conditions The switchover from normal 5V to 5VSTDBY is fully automatic whichever voltage is higher will be available to the RTC As a second alternative...

Страница 70: ...300016 Access Mode Byte only Supported Transfers Byte only 4 LSB Battery Type CR2032 Interrupt Request Level Software programmable FGA 002 Interrupt Request Channel Local IRQ 0 SW11 1 SW11 3 Default...

Страница 71: ...Features of the DUSCC Dual full duplex synchronous asynchronous receiver and transmitter Multiprotocol operation consisting of BOP HDLC ADCCP SDLC SDLC Loop X 25 or X 75 link level COP BISYNC DDCMP X...

Страница 72: ...018 FF802019 FF80201A FF80201C 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1C 00 00 00 00 00 00 00 00 00 R W R W R W R W R W R W R W R W R W R W R W R W R R R W R...

Страница 73: ...CR DUSOMR DUSCTH DUSCTL DUSPCR DUSCCR DUSTFIFO DUSRFIFO DUSRSR DUSTRSR DUSICTSR DUSIER Channel Mode Reg 1 Channel Mode Reg 2 SYN1 Secondary Adr Reg 1 SYN2 Secondary Adr Reg 2 Transmitter Parameter Reg...

Страница 74: ...218 FF802219 FF80221A FF80221C 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1C 00 00 00 00 00 00 00 00 00 R W R W R W R W R W R W R W R W R W R W R W R W R R R W R...

Страница 75: ...CR DUSOMR DUSCTH DUSCTL DUSPCR DUSCCR DUSTFIFO DUSRFIFO DUSRSR DUSTRSR DUSICTSR DUSIER Channel Mode Reg 1 Channel Mode Reg 2 SYN1 Secondary Adr Reg 1 SYN2 Secondary Adr Reg 2 Transmitter Parameter Reg...

Страница 76: ...eiver hybrid sockets For reference the switches and hybrids are assigned to the serial ports according to the following table 3 9 5 RS 232 and RS 422 485 Driver Modules In order to conserve board spac...

Страница 77: ...F default RS 232 support for port 3 FH 002 hybrid must be installed for J124 ON RS 422 485 support for port 3 FH 003 hybrid must be installed for J124 SW12 3 Description OFF default RS 232 support for...

Страница 78: ...CTS x x x x x x x x C29 C30 C31 C32 A32 A29 A30 A31 Data Carrier Detect Receive Data Transmit Data Data Terminal Ready Signal GND supplied by FH 002 Data Set Ready Request to Send Clear to Send Port...

Страница 79: ...puts Each port occupies the same nine pins of the D Sub connector as in the RS 232 compatible configuration but with a different signal association When a serial port is configured for RS 422 operatio...

Страница 80: ...Device 68562 DUSCC Access Address FF80 200016 Port Width Byte Interrupt Request Level Software programmable FGA 002 Interrupt Level Local IRQ 4 Port Signal Input Output VME Connector P2 Description 1...

Страница 81: ...erating system oriented timer The parallel interfaces operate in unidirectional or bidirectional modes either 8 or 16 bits wide The PI T contains a 24 bit wide counter and a 5 bit prescaler 3 10 1 Fea...

Страница 82: ...FF800C10 FF800C11 FF800C12 FF800C13 FF800C14 FF800C15 FF800C16 FF800C17 FF800C18 FF800C19 FF800C1A 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 10 11 12 13 14 15 16 17 18 19 1A 00 00 00 00 00 00 00 00 0...

Страница 83: ...n relation to the rotary switch signals 1 reserved H1 H2 H3 H4 User I O via optional B5 or optional 5 row VME P2 connector I I O I I O PB0 PB1 PB2 PB31 PB41 PB5 PB6 PB7 Floppy Disk Drive Control DMA C...

Страница 84: ...s the rotary switches for automatic configuration 3 10 5 Floppy Disk Drive Control Lines at PI T 1 PB0 PB5 These lines control the FDC37C65C floppy disk drive interface They perform the functions list...

Страница 85: ...ORY OPTION This 8 bit input port may be available as a factory option at the 16 pin connector B5 and may be available as a factory option at the 5 row VME P2 connector Four bits are connected to port...

Страница 86: ...errupt channel Therefore they will generate interrupts at the same interrupt priority level and the user s software may need to poll the PI T device to determine the actual cause of the interrupt For...

Страница 87: ...X Reset Value Label Description FF800E00 FF800E01 FF800E02 FF800E03 FF800E04 FF800E05 FF800E06 FF800E07 FF800E08 FF800E09 FF800E0A FF800E0B FF800E0C FF800E0D FF800E10 FF800E11 FF800E12 FF800E13 FF800E...

Страница 88: ...of PI T 2 This port can be used to build a Centronics type interface Table 28 PI T 2 Interface Signals Pin Function In Out PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 User I O via optional B6 or optional 5 row V...

Страница 89: ...t is defined 3 10 16 Board Identification at PI T 2 PB3 PB7 From these lines the CPU board identification number can be read in by software Every CPU board has a unique number Different versions of on...

Страница 90: ...ser s software for example a background system task would constantly restart the timer Should the timer fail to be restarted the PI T will generate a low level on the Timer Interrupt Request output pi...

Страница 91: ...I T 2 PC5 This line controls the local devices when a DMA transfer is in progress When the DMA controller accesses a local device SCSI or FDC this line must be set to 0 SEE ALSO There are two other DM...

Страница 92: ...he System PROM Area on page 42 and to Section 3 6 1 4 Programming Flash Devices on page 47 3 10 23 Reserved Lines at PI T 2 PC7 These lines are not used In order to retain compatibility with earlier a...

Страница 93: ...al time monitor debugger VMEPROM 3 11 1 Features of the 87033 34 SCSI Controller Functional superset of the MB87031 SCSI Controller Direct interface to SCSI bus devices with on chip drivers Full suppo...

Страница 94: ...and 7 for arbitration overhead If the data transfer rate is less than 4 Mbyte s the percentage range of CPU operation increases and the DMAC range decreases while the overhead of 7 remains unchanged...

Страница 95: ...d to the target The initiator may arbitrate for the SCSIbus and select a particular target The target may request the transfer of COMMAND DATA STATUS or other information on the data bus and in some c...

Страница 96: ...4 3SCSIbus Terminator Power The power for the terminator of any SCSI device will be provided from the CPU board directly or from the SCSIbus itself If termination power is not delivered from any othe...

Страница 97: ...or 5 1 4 single and double density Programmable stepping rate 2 to 6 ms 3 12 2 Address Map of the FDC The registers of the FDC are accessible via the 8 bit local I O bus byte mode The following table...

Страница 98: ...the used local devices PI T 1 Port B bits 6 and 7 control the local devices in case of direct memory access DMA The following table shows which bit selects the direction of the DMA transfer and which...

Страница 99: ...DMA WORKS WITH FDC BSET 06 PI_T1 PBDR A4 SELECT TRANSFER FDC TO DMA THE FOLLOWING AUX VALUES ARE FOR CPU 30 ONLY MOVE B 00 FGA02 AUXPINC AUX PIN CONTROL MOVE B 07 FGA02 AUXSST AUXSRCSTART MOVE B 03 F...

Страница 100: ...ve contains a jumper which connects the floppy disk drive frame electrically with DC ground insertion of this jumper is not allowed and can cause damage 3 12 9 Summary of the Floppy Disk Controller De...

Страница 101: ...face Compatibility to IEEE 802 3 Ethernet Data rate of 10 Mbit per second DMA capability Interrupt generation 64 Kbytes of Local Buffer RAM 3 13 1 1Ethernet Address A 48 bit Ethernet address has been...

Страница 102: ...AM7990 LANCE data sheet in Section 4 Circuit Schematics and Data Sheets on page 115 3 13 2 1Address Map of the LANCE Registers The LANCE contains one Register Address Pointer RAP and four Control Sta...

Страница 103: ...3 specifications Crystal controlled Manchester Encoder Manchester Decoder acquired clock data within four bit times with an accuracy of 3 ns Guaranteed carrier and collision detection squelch thresho...

Страница 104: ...or providing a quick and secure connection to an Ethernet cable 3 13 5 The LAN Buffer RAM LAN Buffer RAM is accessible from addresses FEF0 000016 to FEF0 FFFF16 and the port width is 16 bits word The...

Страница 105: ...function which is described in the Boot Software description of the FGA 002 User s Manual The Reset Function can be controlled by switch SW7 1 3 14 2 ABORT Function Switch An interrupt on a software...

Страница 106: ...hexadecimal encoded These switches are completely under software control The default setting is FF16 SEE ALSO For a detailed description of the use of these switches under VMEPROM please refer to Sect...

Страница 107: ...from 1 through 7 The Gate Array may supply the interrupt vector or it may initiate an interrupt vector fetch from the I O device or from the VMEbus In addition to local interrupts the ACFAIL and SYSFA...

Страница 108: ...ld low during this cycle while the data strobe signals are driven low twice once for the read cycle and once for the write cycle and high between the both of them All seven VMEbus interrupt request si...

Страница 109: ...ve transfers automatically so that no overhead in software is necessary The following table lists the VMEbus address ranges and their associated address and data bus sizes in detail SEE ALSO For furth...

Страница 110: ...er ranges as shown in the following table 1 RMW Read Modify Write 1 RMW Read Modify Write Table 31 Defined VMEbus Transfer Cycles D32 Mode Transfer Type D31 D24 D23 D16 D15 D08 D07 D00 Byte Byte X X W...

Страница 111: ...H H H H H H H H H H H H L L L L H H L L H H L L H L H L H L H L Standard Supervisory Block Transfer Standard Supervisory Program Access Standard Supervisory Data Access Reserved Standard Non Privilege...

Страница 112: ...ser Defined User Defined 0F 0E 0D 0C 0B 0A 09 08 L L L L L L L L L L L L L L L L H H H H H H H H H H H H L L L L H H L L H H L L H L H L H L H L Extended Supervisory Block Transfer Extended Supervisor...

Страница 113: ...F16 VMEbus Standard Access A24 D32 D24 D16 D8 111110 111101 111010 111001 3E16 3D16 3A16 3916 SPA SDA NPA NDA FBFF 000016 FBFF FFFF16 VMEbus Short I O Access A16 D32 D24 D16 D8 101101 101001 2D16 2916...

Страница 114: ...slave access to the Shared RAM from the VMEbus only Extended Address A32 accesses are allowed The on board logic allows accesses in the Privileged supervisor or Non Privileged user mode for both data...

Страница 115: ...VMEbus interrupt request level can be mapped to cause an interrupt to the processor on a different level So for example a VMEbus interrupt request on level 2 IRQ2 can be mapped to cause an interrupt r...

Страница 116: ...must be disabled if the CPU board is located in any other slot When the on board single level VMEbus arbiter is enabled all other VMEbus masters if any must request VMEbus master ship using only bus r...

Страница 117: ...release functions have no impact don t care The REC mode is only for CPU cycles to the VMEbus and not for cycles initiated by the on board DMA controller The programming of the REC mode is described i...

Страница 118: ...MEbus and not for cycles initiated by the on board DMA controller Programming of the RBCLR mode is described in the FGA 002 Gate Array User s Manual 3 20 3 5Release When Done RWD The DMA Controller wi...

Страница 119: ...ee remaining Bus Grant signals BG0 BG1 BG2 to a high level SEE ALSO For a detailed description of the slot 1 detection please refer to Section 3 21 Slot 1 Detection on page 107 1 Don t Care Table 37 B...

Страница 120: ...hen the CPU 30 R4 is plugged into slot 1 it will succeed in pulling the VME signal to a low signal level because Bus Grant In Level 3 is floating on slot 1 Hence the CPU 30 R4 detects slot 1 When the...

Страница 121: ...bled on the backplane This is not necessary on active backplanes 3 21 2 Slot 1 Status Register The status of the slot 1 detection may be read via the Slot 1 Status Register at FF80 398016 It is a read...

Страница 122: ...etected after a timeout period In addition to the FGA 002 Gate Array Bus Timer the CPU 30 R4 provides an additional VMEbus Timer This timer can be enabled when the CPU 30 R4 provides System Controller...

Страница 123: ...I O boards The FGA 002 drives the SYSFAIL signal after reset and until initialization of the board is completed For compatibility with other VME boards this signal can be enabled and disabled by the s...

Страница 124: ...o the reset register within the FGA 002 Optional watchdog timer from PI T 2 expires Power up condition Voltage monitor module detects a low voltage condition on the CPU 30 R4 3 22 3 The ACFAIL Signal...

Страница 125: ...tch The RUN LED is red while the reset generator drives the on board reset signal After reset the LED light will change to green The upper switch on the front panel of the CPU board is the RESET switc...

Страница 126: ...s as a reset generator Power up reset is provided by this sensor as soon as the supply voltage Vcc has reached approximately 3 volts The local reset signal will be asserted if Vcc subsequently falls b...

Страница 127: ...Hardware Description SYS68K CPU 30 R4 Technical Reference Manual Page 114...

Страница 128: ...heets Page 115 4 Circuit Schematics and Data Sheets 4 1 Circuit Schematics of SYS68K CPU 30 R4 Copies of the CPU 30 R4 schematics are found on the next page The schematics contain the signal and unit...

Страница 129: ...2 List of Data Sheets This is a list of the data sheets which are relevant to the SPARC CPU 30 R4 Copies of these data sheets are found on the following pages RTC 72421 DUSCC 68562 PI T TS68230 SCSI...

Страница 130: ...SYS68K CPU 30 R4 Technical Reference Manual Set of Data Sheets Page 117 4 2 1 RTC 72421...

Страница 131: ...Set of Data Sheets SYS68K CPU 30 R4 Technical Reference Manual Page 118 4 2 2 DUSCC 68562...

Страница 132: ...SYS68K CPU 30 R4 Technical Reference Manual Set of Data Sheets Page 119 4 2 3 PI T TS68230...

Страница 133: ...Set of Data Sheets SYS68K CPU 30 R4 Technical Reference Manual Page 120 4 2 4 SCSI 87033 34...

Страница 134: ...SYS68K CPU 30 R4 Technical Reference Manual Set of Data Sheets Page 121 4 2 5 FDC37C65C...

Страница 135: ...Set of Data Sheets SYS68K CPU 30 R4 Technical Reference Manual Page 122 4 2 6 LANCE Am79C90...

Страница 136: ...SYS68K CPU 30 R4 Technical Reference Manual Set of Data Sheets Page 123 4 2 7 SIA Am7992B...

Страница 137: ...Set of Data Sheets SYS68K CPU 30 R4 Technical Reference Manual Page 124 4 2 8 Motorola MC68030 and MC68882...

Страница 138: ...display and modify Display and modify floating point data registers S record up downloading from any port defined in the system Time stamping of user programs Built in Benchmarks Support of RAM disk a...

Страница 139: ...he VMEPROM banner and the VMEPROM prompt will be displayed upon power up or reset The default terminal port setup is as follows Asynchronous communication 9600 Baud 8 data bits 1 stop bit No parity Ha...

Страница 140: ...el of VMEPROM If ABORT is pressed while a user program is under execution all user registers are saved at the current location of the program counter and the message Aborted Task is displayed along wi...

Страница 141: ...for detailed description Table 39 Lower Rotary Switch SW1 Bit 3 and Bit 2 These two bits define which program is to be invoked after reset Please refer to Table 41 Program After Reset on page 129 for...

Страница 142: ...r UNIX mailbox driver 0 4 8 C Table 43 Examples in Using the Rotary Switches Rotary Switches Description Upper Lower F F No RAM Disk initialization will be done The VMEbus data size is 32 bits The RAM...

Страница 143: ...000016 0000 03FF16 Vector Table 0000 040016 0000 0FFF16 System Configuration Data 0000 100016 0000 5FFF16 SYRAM 0000 600016 0000 6FFF16 VMEPROM internal use 0000 700016 0000 7FFF16 Task Control Block...

Страница 144: ...System Tools Debugging Tools Line Assembler Disassembler FF03 600016 FF03 CFFF16 UNIX V 3 PDOS Boot Program FF03 D00016 FF03 FFFF16 reserved FF04 000016 FF07 FFFF16 Flash Programming Utility FF08 000...

Страница 145: ...VMEPROM SYS68K CPU 30 R4 Technical Reference Manual Page 132...

Страница 146: ...All interrupt levels and vectors of the on board I O devices are software programmable via the FGA 002 Gate Array Table 46 On board I O Devices Base Address Device FF80 0C0016 PI T1 68230 FF80 0E0016...

Страница 147: ...rder to ensure that these boards work correctly with VMEPROM the listed interrupt vectors must not be used 6 4 The On board Real Time Clock During the power up sequence the on board Real Time Clock of...

Страница 148: ...on 2 5 Serial I O Channels on page 21 and to Section 3 9 The DUSCC 68562 on page 58 for the pinning of the D Sub connector and the required handshake signals See Table 1 Specifications for the CPU 30...

Страница 149: ...ns of VMEPROM All the common commands of VMEPROM are described in detail in the VMEPROM User s Manual Those commands which are specific for the hardware of the CPU board are described in the following...

Страница 150: ...d Format ARB The ARB command allows the user to set the arbitration and release modes of the CPU board for the VMEbus Additionally the VMEbus interrupts can be enabled or disabled Example ARB Set arbi...

Страница 151: ...ported boards in Section 9 Appendix to VMEPROM on page 149 Additional memory must be contiguous to the on board memory of the CPU board This memory is cleared by the config command to allow DRAM board...

Страница 152: ...ze of one erasable region is 256 Kbyte 64 KB 4 The parameters are used as follows flashbank Symbolic name or base address of the Flash Memory bank that should be erased The following symbolic names ar...

Страница 153: ...in binary format If only a CR is entered no change will be made To step backward a minus has to be entered If a or ESC is given the FGA command returns to the shell NOTE The command uses cursor posit...

Страница 154: ...uffered write mode for the local SCSI controller If no argument is entered all modified hashing buffers are flushed If an argument of ON or OFF is given the buffered write mode will be enabled or disa...

Страница 155: ...rs Slot numbers can range from 0 to 21 A slot number of 0 sends the message to all slots The second parameter defines which FMB channel should be used It can be 0 or 1 The message is the byte to be de...

Страница 156: ...grams all the remaining space from offset to end of flash bank The third format of the command also specifies the number of bytes to program The parameters are used as follows flashbank Symbolic name...

Страница 157: ...Data Bus Width of the VMEbus Format MEM MEM 16 MEM 32 This command can display or set the data bus width of the CPU board on the VMEbus If no argument is entered the current data bus width is displaye...

Страница 158: ...y disk controller and the SCSI controller proceeds as expected 2 Memory Test on the Memory of the Current Task The following procedures are performed 1 Byte Test 2 Word Test 3 Longword Test All passes...

Страница 159: ...e following example aids in formatting a CDC 94211 5 Winchester FRMT 68K PDOS Force Disk Format Utility Possible Disk Controllers in this System are Controller 1 is not defined Controller 2 is a FORCE...

Страница 160: ...0 10219 Ready to FORMAT Winchester Drive 0 Y Sector Interleave Table 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Issuing Format Drive Command FORMAT SUCCESSF...

Страница 161: ...28 2336 15 9498 9577 9498 9577 2528 2336 16 9578 9657 9578 9657 2528 2336 17 9658 9737 9658 9737 2528 2336 18 9738 9817 9738 9817 2528 2336 19 9818 9897 9818 9897 2528 2336 20 9898 9977 9898 9977 2528...

Страница 162: ...to the on board memory 9 1 2 SYS68K SIO 1 2 These two serial I O boards are set to the VME base address B0 000016 by default VMEPROM expects the first SIO 1 SIO 2 boards at FCB0 000016 This is in the...

Страница 163: ...dware configuration must be detected before a port can be installed This can be done with the CONFIG command or by setting a front panel switch on the CPU Board and pressing RESET Please refer to the...

Страница 164: ...O board in VMEPROM the BP command can be used The ISIO 1 2 boards are driver type 3 In order to install the first port of an ISIO board with a 9600 baud rate the following command line can be used The...

Страница 165: ...ity The step rate is 3 ms The Winchester drives are not installed automatically The VMEPROM FRMT command must be used for defining the following factors The physical drive structure i e number of head...

Страница 166: ...the Winchester drive The partitions to be used If this setup is done once for a particular drive the data is stored in the first sector of the Winchester and is loaded automatically when the disk con...

Страница 167: ...data and the 3 byte address at which the code data is to reside S3 A record containing code data and the 4 byte address at which the code data is to reside S5 A record containing the number of S1 S2...

Страница 168: ...B241F8044CB1 S214020010203C0000020E428110C1538066FA487AE4 S214020020001021DF0008487A001221DF000C4E750E S21402003021FC425553200030600821FC41444452C2 XX Check sum XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Data 0...

Страница 169: ...NTM NM define NTP NP define NCB NC define NFS NF define NEV ND define NIE ND 2 define NPS NU 1 define P2P IZ define MMZ MZ define TMZ TZ define IMK 0xFF 8 P2P input buffer wrap around mask define NCP...

Страница 170: ...har _tltp task list pointer 0B0 char _utcb user tcb ptr 0B4 int _suim supervisor interrupt mask 0B6 int _usim user interrupt mask 0B8 char _sptn spawn task no must be even 0B9 char _utim user task tim...

Страница 171: ...har _tlst NTB TBZ task list 1DEA char _tsev NTB 32 task schedule event table 25EA long _tmtf NTM to from INDEX W 26EA char _tmbf TMZ NTM task message buffers 36EA char _tmsp NTP 6 task message pointer...

Страница 172: ...isters are stored in the following order define VBR 0 define SFC 1 define DFC 2 define CACR 4 define PC 5 define SR 6 define USTACK 7 define SSTACK 8 define MSTACK 9 define D0 10 10 17 D0 D7 define A0...

Страница 173: ...ress 44A char _cmd command line delimiter 44B BYTE _tid task id 44C char _ecf echo flag 44D char _cnt output column counter 44E char _mmf memory modified flag 44F char _prt input port 450 char _spu sp...

Страница 174: ...c 7FC char VMEMSP 202 Master stack handle w care 8C6 char VMESSP 802 supervisor stack handle w care BE8 char VMEPUSP 802 vmeprom internal user stack F0A LWORD f_fpreg 3 8 floating point data regs F6A...

Страница 175: ...6 02416 Trace 10 0A16 02816 VMEPROM System Calls 11 0B16 02C16 Coprocessor Instructions 12 0C16 03016 Unassigned Reserved 13 0D16 03416 Coprocessor Protocol Violation 14 0E16 03816 Format Error 15 0F1...

Страница 176: ...fined Vectors 119 7716 1DC16 Disk Interrupt Vector ISCSI 1 120 191 7816 BF16 1E016 2FC16 User Defined Vectors 192 C016 30016 Mailbox 0 193 C116 30416 Mailbox 1 194 C216 30816 Mailbox 2 195 C316 30C16...

Страница 177: ...3B816 Reserved 239 EF16 3BC16 Reserved 240 F016 3C016 LOCAL1 241 F116 3C416 LOCAL2 242 F216 3C816 LOCAL3 243 F316 3CC16 LOCAL4 244 F416 3D016 LOCAL5 245 F516 3D416 LOCAL6 246 F616 3D816 LOCAL7 247 F71...

Страница 178: ...EN7END xdef BEN8BEG BEN8END xdef BEN9BEG BEN9END xdef BEN10BEG BEN10END xdef BEN11BEG BEN11END xdef BEN12BEG BEN12END xdef BEN13BEG BEN13END xdef BEN14BEG BEN14END page benchmark execution benchex add...

Страница 179: ...1 D3 012 DBEQ D1 010 BNE S 090 MOVE L A0 A2 MOVE L A1 A3 MOVE W D0 D4 BMI S 030 020 CMP B A2 A3 DBNE D4 020 BNE S 012 030 SUB W D1 D2 032 MOVEM L A7 D3 D4 A2 A3 RTS 090 MOVEQ L 1 D2 BRA S 032 END EDN...

Страница 180: ...OVEQ L 1 D0 MOVE W 123 D1 BSR S EDN2 SUBQ L 1 D4 BNE S 010 RTS EDN2 SUB W 2 D0 BEQ S 020 SUBQ W 1 D0 BEQ S 030 010 BFTST A0 D1 1 DC W E8D0 DC W 0841 SNE D2 RTS 020 BFSET A0 D1 1 DC W EED0 DC W 0841 SN...

Страница 181: ...B 00000001 DC B 01110010 DC B 10000000 EVEN PAGE BENCH 6 CACHE TEST 128KB PROGRAM IS EXECUTED 1000 TIMES CAUTION THIS BENCHMARK NEEDS 128 KBYTE MEMORY LEA L 010 PC A2 MOVE L 203A0000 D1 OPCODE FOR MO...

Страница 182: ...L 1 FP1 010 FMUL X FP0 FP1 SUBQ L 1 D5 BNE S 010 RTS PAGE PDOS BENCHMARK 1 CONTEXT SWITCHES MOVE L 100000 D6 000 XSWP CONTEXT SWITCH SUBQ L 1 D6 DONE BGT S 000 N RTS PAGE PDOS BENCHMARK 2 EVENT SET MO...

Страница 183: ...SK MESSAGE CLR L D0 SELECT TASK 0 LEA L MES01 PC A1 POINT TO MESSAGE MOVE L 100000 D6 000 XSTM SEND MESSAGE XKTM READ MESSAGE BACK SUBQ L 1 D6 DONE BGT S 000 N RTS MES01 DC B BENCH 13 0 EVEN PAGE PDOS...

Страница 184: ...the System Flash into a file First copy the binary image to the local RAM of the other CPU board via the VMEbus BM FF000000 FF400000 destination Then save it to disk Now the on board System Flash can...

Страница 185: ...00016 These four entries contain the address which is jumped to after kernel initialization This can be selected by bits 3 and 2 of the Lower Rotary Switch The second entry contains the address of the...

Страница 186: ...0 00 00 00 00 00 00 SY STRT FF00E010 00 00 00 00 00 00 00 08 08 00 40 80 00 00 00 08 FF00E020 08 00 40 70 00 00 00 08 08 00 FC 80 00 00 53 59 p SY FF00E030 24 44 53 4B 00 00 00 00 00 00 00 00 00 00 00...

Страница 187: ...ack pointer has to be set to point to an appropriate address in RAM 9 8 3 Using System Flash Memory Since VMEPROM image needs about 512 Kbytes of the System Flash memory there are still 3 5 Mbytes of...

Страница 188: ...to VMEPROM Page 175 SEE ALSO For further information please refer to Table 45 Layout of System Flash Memory on page 130 Now the modified image can be programmed into System Flash as described in Secti...

Страница 189: ...Appendix to VMEPROM SYS68K CPU 30 R4 Technical Reference Manual Page 176...

Страница 190: ...If no program modules are found the debugger will be started instead To start the debugger manually both Rotary Switches must be set to F and the Abort Switch must be kept asserted while reset The sta...

Страница 191: ...ides at address FFE0 000016 Check if Abort Switch is asserted abort Read board ID from port Initialize CPU registers enable caches Initialize the front panel serial I O port 1 Initialize the PIT devic...

Страница 192: ...le variable firmwarebase firmwaremodule BOOT_ROM2 firmwaremodule SystemFlash Set startModule OK assume firmwaremodule is executable see Note 1 see Note 2 while 1 abort startModule ERROR N Y abort new...

Страница 193: ...ute address 3 An disassembles the same location again 4 A or Return disassembles the next location 5 A or sign followed by the number of bytes increases decreases the address counter 6 A or ESC allow...

Страница 194: ...R entry address stored at offset 3016 of the booter or via an exception for setting a vector use the address stored at offset 3416 of the booter image All registers will be restored before leaving the...

Страница 195: ...ssembly enter Return or to abort enter any other key The disassembler supports all 68020 30 40 mnemonics and the 68881 82 floating point instructions Example 10 4 DRAMINIT Initialize DRAM Format DRAMI...

Страница 196: ...lows flashbank Symbolic name or base address of the Flash Memory bank that should be erased The following symbolic names are currently supported BOOT_FLASH first BOOT FLASH BOOT_FLASH1 first BOOT FLAS...

Страница 197: ...sh Memory bank and programs all the remaining space from offset to end of flash bank The third format of the command also specifies the number of bytes to program The parameters are used as follows fl...

Страница 198: ...OOT FPROG Usage FPROG flashbank source flashoffset length Parameter flashbank is the base address of the flash bank or one of the following defines BOOT_FLASH1 BOOT_FLASH2 SYS_FLASH1 FORCE BOOT FPROG...

Страница 199: ...d format contains parameter offset that specifies the value that is added to the absolute addresses of the S Records This allows to modify the storage address while the download The next two formats a...

Страница 200: ...Ether net number 2 After the board has received its own IP number a TFTP request is sent to this server which has replied the RARP The server now starts sending the requested file On a UNIX system the...

Страница 201: ...en FORCE BOOT NETLOAD test 100000 00 80 42 03 88 88 LAN controller at address FEF80000 set to Ethernet 00 80 42 03 88 88 Transmitting RARP REQUEST LAN controller at address FEF80000 set to Ethernet 00...

Страница 202: ...rt Module at Address FFFF FFFF16 The user can specify the address of a program module here A module must pro vide a SSP stack pointer at offset 0 and a PC program counter at offset 4 If a value of FFF...

Страница 203: ...This can be done by modifying the value of CTL1 via command SETUP After setting a new slot number the INIT command must be executed to recalculate the SRAM checksum and validate the new values Exampl...

Страница 204: ...e following example sets the VMEbus slave address of the board to 8300 000016 and the window size to 1 Mbyte It can now be accessed from 8300 000016 to 830F FFFF16 FORCE BOOT VMEADDR 83000000 100000 U...

Страница 205: ...the stack as last one must contain the number of the requested function the rest of the parameters depends on the specified function NOTE The utility interface must be called in supervisor mode It wi...

Страница 206: ...36 flashbank source offset length Parameters flashbank Base address of the Flash Memory bank that should be programmed source Source address of the data to program offset Relative byte offset within...

Страница 207: ...ytes If length is 0 all the remaining space of the flash bank will be erased If offset and length are both set to 0 the whole flash bank is erased Returns 0 OK 1 CLEAR_ERROR 2 INVAL_PARMS 3 ERASE_ERRO...

Страница 208: ...where the System Values start in SRAM typedef packed struct ULONG startModule SYS_VALUES Returns size of struct in bytes 39 0x27 Get Application Values in SRAM This function sets a pointer to the base...

Страница 209: ...rd s Ethernet number 6 bytes to the specified buffer The return value contains the status of this operation Syntax long util 40 intfNumb pEtherAdr Parameters intfNumb Interface number must be set to 0...

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