Force SYS68K/CPU-30 R4, Техническое справочное руководство

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Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual
Page 84
3.12 The Floppy Disk Controller
The CPU board contains a single chip floppy controller, the
FDC37C65C. The FDC is connected to the DMA controller of the
FGA-002 Gate Array. The installed driver/receiver circuits allow direct
connection of 3 1/2" and 5 1/4" inch floppy drives. All I/O signals are
available on the VMEbus P2 connector. The I/O signal assignment is
compatible to the SYS68K/ISCSI-1 controller, which allows the use of
the SYS68K/IOBP-1 and IOPI-2 for interconnection to mass storage
devices.
3.12.1 Features of the
FDC37C65C
Controller
- Built-in data separator
- Built-in write precompensation
- 128-, 256-, 512- or 1024-byte sector lengths
- 3 1/2" or 5 1/4" single and double density
- Programmable stepping rate (2 to 6 ms)
3.12.2 Address Map
of the FDC
The registers of the FDC are accessible via the 8 bit local I/O bus (byte
mode). The following table shows the register layout of the FDC37C65C
for the CPU-30 R4.
SEE ALSO: Additional information is provided in the FDC37C65C data
sheet included in Section 4, ‘Circuit Schematics and Data Sheets,’ on
page 115.
3.12.3 Data Rate
Support
The FDC37C65C allows two Data Rate Selection Options controlled via
the Data Rate Selection Register. The CPU-30 R4 supports the 16 MHz
and 9.6 MHz options.
SEE ALSO: For further details please refer to Section 4, ‘Circuit
Schematics and Data Sheets,’ on page 115.
FF80.3800
16
Read Main Status Register
(Write is illegal)
FF80.3801
16
Read Data Register
Write Date Register
FF80.3880
16
Read DCHG Register
Write Data Rate Selection Register
FF80.3900
16
Write Digital Output Register
(Read is illegal)
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