Force SYS68K/CPU-30 R4, Техническое справочное руководство

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SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description
Page 37
3.4 The Local Bus
3.4.1 The FGA-002
Gate Array The CPU board also contains the FGA-002 Gate Array with 24,000 gates
and 304 pins.
The FGA-002 Gate Array controls the local bus and builds the interface
to the VMEbus. It also includes a DMA controller, complete interrupt
management, a message broadcast interface (FMB), timer functions, and
mailbox locations.
The gate array monitors the local bus. This in turn signifies that if any
local device is to be accessed, the gate array takes charge of all control
signals in addition to used address and data signals.
The FGA-002 Gate Array serves as a manager for the VMEbus. All
VMEbus address and data lines are connected to the gate array through
the buffers. Additional functions such as the VMEbus interrupt handler
and arbiter are also installed on the FGA-002 Gate Array.
The start address of the FGA-002 Gate Array registers is FFD0.0000
16
.
All registers of the gate array and associated functions are described in
detail in the FGA-002 Gate Array User’s Manual.
3.4.2 Shared DRAM The CPU board contains a Shared dynamic RAM area with a capacity of
4, 8, 16 or 32 Mbytes. The Shared RAM area is optimized for fast
accesses from the 68030 CPU and the DMA controller in the FGA-002
Gate Array. The Shared RAM is also accessible by other VMEbus
masters.
The Shared RAM area is arranged in 36-bit wide memory banks. There
may be one or two of these banks on the CPU board, depending on the
overall memory capacity delivered. Each 36-bit wide bank is separated
into 32 data bits and 4 parity bits. A parity bit checks every eight
consecutive data bits (byte parity). Advanced on-board memory control
logic routes data to and from the on-board 68030 CPU, the DMA
controller, and the VMEbus interface.
For every read cycle, regardless of size (byte, word, long-word or cache
line) and regardless of master (68030, DMA or VMEbus), all 32 bits of
data and 4 bits of parity are read from the Shared RAM array. The 32 data
and 4 parity bits are stored in transceivers.
Parity is regenerated in FGA-002 and compared to the parity bits read
from memory. If a mismatch is found on an accessed byte, an error will
be flagged. A synchronous termination signal (STERM) is asserted, and
the cycle completes.