Force SYS68K/CPU-30 R4, Техническое справочное руководство

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SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description
Page 41
The first read cycle of such a burst usually requires 5 CPU clock cycles
(200 nanoseconds at 25 MHz). Due to the optimized design of the
memory control logic, each subsequent cycle only requires 1 CPU clock
cycle (40 nanoseconds) to complete. This is commonly called a "5-1-1-1"
burst transfer. Overall, the total cache line "burst fill" operation requires 8
clock cycles to transfer 16 bytes, providing a memory bandwidth of over
50 Mbytes/second.
Not all CPU accesses are burst transfers. Single read and write
transactions are also supported at the fastest possible speed. A single read
or write access (1, 2, or 4 bytes) requires 5 CPU clock cycles. Distributed
asynchronous refresh is provided every 14 microseconds and an access
during a pending refresh cycle may be delayed by a maximum of five
additional clock cycles.