Force SYS68K/CPU-30 R4, Техническое справочное руководство

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SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description
Page 95
3.16 VMEbus Interface
The CPU board contains a complete VMEbus interface which is
compatible with the IEEE 1014 standard (VMEbus Revision C).
The VMEbus interface supports 8, 16, 32 bit, and unaligned data
transfers. The extended, standard, and short I/O address modifier codes
are implemented to interface to all existing VMEbus products.
Read-Modify-Write cycles on the VMEbus are also supported. The
address strobe signal is held low during this cycle while the data strobe
signals are driven low twice, once for the read cycle and once for the
write cycle, and high between the both of them.
All seven VMEbus interrupt request signals are monitored by the
FGA-002 which can optionally map every level and then interrupt the
local CPU. A single level bus arbiter together with several release
functions are implemented with all "Slot-1" system controller functions
such as SYSRESET* driver and receiver, SYSCLK driver, and IACK
daisy-chain driver.
The following sections describe the functions of the interface parts in
detail.
For the connections to the IOBP-1 back panel, please refer to
Section 2.11, ‘The SYS68K/IOBP-1,’ on page 26.