Force SYS68K/CPU-30 R4, Техническое справочное руководство

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SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description
Page 77
3.10.17 Interrupt
Request Signal
of PI/T #2
TOUT:
PI/T #2 pin PC3 is used as a Timer Interrupt Request output. The 24-bit
timer can generate interrupt requests at a software programmable
interval. The Timer Interrupt Request line is connected to the local IRQ
#3 of the FGA-002. Optionally, the Timer Interrupt Request may be used
as a "watchdog" reset generator.
If the PI/T #2 Timer Interrupt Request line is connected as a watchdog
reset generator, then the user can program the 24-bit timer to generate a
local hardware reset whenever the timer counts down to zero. This allows
the user to implement a simple watchdog timer. In normal operation, the
timer would never expire. Instead, the user's software (for example, a
background system task) would constantly restart the timer. Should the
timer fail to be restarted, the PI/T will generate a low level on the Timer
Interrupt Request output pin. That will trigger the Reset Generator,
resetting the entire CPU board. The watchdog reset generator option is
enabled and disabled via a switch at location SW13-2.
NOTE: There is another timer interrupt signal at PI/T #1 which doesn’t
have anything to do with these signals of PI/T #2.
3.10.18 PC0-PC1
Hardware ID
at PI/T #2
To allow simple detection of different hardware implementations, a
hardware ID-number can be read in on the PI/T #2 pins PC0-PC1.
3.10.19 Floppy Drive
Ready Signal at
PI/T #2
PC2:
From this line the status of the write protection for the Boot PROM
devices may be monitored.
SW13-2 Description
OFF (default) Watchdog Timer Disabled
ON Watchdog Timer Enabled
PC1 PC0 Description
1 1 Revision 1, 2, 3
1 0 Revision 4
0 1 Reserved
0 0 Reserved
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