Force SYS68K/CPU-30 R4, Техническое справочное руководство

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SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description
Page 109
3.21.4 The SYSCLK
Driver
The CPU board contains all the necessary circuitry to support the
SYSCLK signal. The output signal is a stable 16 MHz signal with a 50%
duty cycle. The driver circuitry for the SYSCLK signal has a current
driver capacity of 64mA.
The SYSCLK signal will be enabled if the board detects slot-1.
3.21.5 VMEbus Timer The FGA-002 Gate Array has implemented a Bus Timer to terminate
VME transfers which initiates a bus error when no acknowledge can be
detected after a timeout-period.
In addition to the FGA-002 Gate Array Bus Timer, the CPU-30 R4
provides an additional VMEbus Timer. This timer can be enabled when
the CPU-30 R4 provides System Controller functions (slot-1 detected).
The additional VMEbus Timer is controlled by switch SW7-4.
The timeout period for the additional VMEbus Timer can be configured
with the switches SW6-1 and SW6-2.
SW7-4 Description
OFF (default) Additional VMEbus Timer enabled if slot-1 detected
(otherwise disabled)
ON Additional VMEbus Timer disabled
SW6-1 SW6-2
Default
Position
Description
OFF OFF x Additional Bus Timer timeout = 83.53 ms
OFF ON Additional Bus Timer timeout = 1.3 ms
ON OFF Additional Bus Timer timeout = 81.6
µ
s
ON ON Additional Bus Timer timeout = 10.2
µ
s