Force SYS68K/CPU-30 R4, Техническое справочное руководство

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SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description
Page 81
The DMA Controller includes a 32-byte FIFO which waits until the 32
bytes are filled and then requests local bus mastership for an eight cycle
data transfer (32 bit in parallel).
In addition to the 32-byte DMA FIFO, the DMA channel includes a
second FIFO (8 bytes deep) to fill the DMA FIFO if the DMA transfer to
main memory is taking place. This allows continuous data transfer on the
local DMA bus with a data rate of 4 Mbyte/s without any timing gaps in
between.
This technique permits the CPU to perform in a real time capacity
because the ratio of CPU and DMA operation at the maximum SCSI data
transfer rate of 4 Mbyte/s is 73% for the CPU, 20% for the DMA
Controller and 7% for arbitration overhead. If the data transfer rate is less
than 4 Mbyte/s, the percentage range of CPU operation increases and the
DMAC range decreases while the overhead of 7% remains unchanged.
3.11.3.1 DMA Control
Lines
Two output pins of PI/T #1 and one output pin of PI/T #2 are used to
control the data direction, to start the DMA Controller, and select the
local peripheral devices.
PI/T #1 Port B bits 6 and 7 control the local devices when DMA transfers
are initiated. The following table shows which bit selects the direction of
the DMA transfer and which bit selects the FDC or SCSI Controller.
Port C bit 5 of PI/T #2 controls the local devices in case of direct memory
access (DMA) as shown in the following table.
The listing below provides a programming example for DMA transfers.
PB7 PB6 Function
0 0 DMA write to SCSI
0 1 DMA read from SCSI
1 0 DMA write to FDC
1 1 DMA read from FDC
PC5 Function
0 DMA active
1 DMA is not active