Force SYS68K/CPU-30 R4, Техническое справочное руководство

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SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description
Page 91
3.13.4.2 The Am7992B
Receiver
The receiver has the responsibility of signalling to the LANCE when
there is a message to receive. It decodes the Manchester-encoded data
stream from the Ethernet cable and sends the data to the LANCE.
SEE ALSO: For further information please refer to the Am7992B data
sheet in Section 4, ‘Circuit Schematics and Data Sheets,’ on page 115.
3.13.4.3 Network
Interface
Configuration
The LAN interface uses a standard 15-pin D-Sub connector providing a
quick and secure connection to an Ethernet cable.
3.13.5 The LAN
Buffer RAM
LAN Buffer RAM is accessible from addresses
FEF0.0000
16
to FEF0.FFFF
16
and the port width is 16 bits (word).
The LAN RAM consists of two 32K * 8-bit SRAMs. These devices can
be accessed by both the CPU and the LANCE after each device arbitrates
for bus mastership.
With this detached memory, it is not necessary for the CPU to stop
processing while the LANCE is bus master and accesses the LAN Buffer
RAM. Thus, the real-time capabilities of the CPU board are preserved.
3.13.6 Summary of
the LAN RAM
Devices 32K * 8 (2x)
Access Address FEF0.0000
16
to FEF0.FFFF
16
Capacity 64 Kbytes
Port Width 16 bits (word)
FGA-002 Interrupt Request Channel Local IRQ #6
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