Force SYS68K/CPU-30 R4, Техническое справочное руководство

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Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual
Page 32
3.2 The CPU 68030 Processor
3.2.1 Hardware
Interface of the
68030 The 68030 uses a nonmultiplexed address and data bus. Asynchronous
signals allow easy interfacing to the outside world; synchronous signals
perform fast interaction.
The CPU drives the address signals (A0-A31), the size signals (SIZ0,
SIZ1) and the function code signals (FC0-FC2) on every cycle,
independent of a cache hit or miss. These signals are used to decode the
memory map of the CPU board.
The hardware on the CPU board is notified by the address and data strobe
signals that the current cycle is not a cache cycle, and that the decoding
outputs are strobed to be valid.
The 32 data lines (D0-D31) are also driven from the processor on write
cycles and sensed on read cycles.
The size of the data transfer is defined by the SIZE + A0 - A1 output
signals (always driven from the CPU). During asynchronous cycles the
data bus width is determined by the Data Size Acknowledge Input signals
(DSACK0, DSACK1). Synchronous cycles acknowledged by the
Synchronous Termination Input signal (STERM) acknowledge the
indicated data width during writes, whereas during reads a 4-byte width
is always acknowledged.
If a bus error occurs (BERR sensed from the CPU), exception handling
starts because the current cycle has been aborted (illegal transfer or
incorrect data).
On local bus operation, a bus error will be generated if a device does not
respond correctly.
VMEbus transfers may also be aborted via a BERR.
3.2.2 The
Instruction Set For the 68030 instruction set and further information relative to
programming, please refer to the 68030 User's Manual.