Epson S1C63656, Техническое руководство

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EPSON
S1C63656 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit)
4.16 SVD (Supply Voltage Detection) Circuit
4.16.1 Configuration of SVD circuit
The S1C63656 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the
source voltage lowers.
Turning the SVD circuit on/off and the SVD criteria voltage setting can be done with software.
Figure 4.16.1.1 shows the configuration of the SVD circuit.
V
Detection output
Data bus
DD
V
SS
SVDON
SVDS2
|
SVDS0
Criteria voltage
setting circuit
SVD circuit
SVDDT
Fig. 4.16.1.1 Configuration of SVD circuit
4.16.2 SVD operation
The SVD circuit compares the criteria voltage set by software and the supply voltage (V
DD
terminal–V
SS
terminal) and sets its results into the SVDDT latch. By reading the data of this SVDDT latch, it can be
determined by means of software whether the supply voltage is normal or has dropped.
The criteria voltage can be selected using the SVDS2–SVDS0 register as shown in Table 4.16.2.1.
Not that the criteria voltage range depends on the selected OSC3 oscillation circuit option (use or not
used).
Table 4.16.2.1 Criteria voltage
SVDS2
1
1
1
1
0
0
0
0
SVDS1
1
1
0
0
1
1
0
0
SVDS0
1
0
1
0
1
0
1
0
When OSC3 is used
2.90
2.75
2.60
2.45
2.30
2.15
2.00
1.85
When OSC3 is not used
1.64
1.56
1.47
1.39
1.30
1.22
1.13
–
Criteria voltage (V)
When the SVDON register is set to "1", source voltage detection by the SVD circuit is executed. As soon as
the SVDON register is reset to "0", the result is loaded to the SVDDT latch and the SVD circuit goes off.
To obtain a stable detection result, the SVD circuit must be on for at least 500 µsec. So, to obtain the SVD
detection result, follow the programming sequence below.
1. Set SVDON to "1"
2. Maintain for 500 µsec minimum
3. Set SVDON to "0"
4. Read SVDDT
When the SVD circuit is on, the IC draws a large current, so keep the SVD circuit off unless it is.