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1 OVERVIEW
S1C31D50/D51 TECHNICAL MANUAL
Seiko Epson Corporation
1-1
(Rev. 2.00)
1 Overview
1.1 Features
The S1C31D50/D51 is a 32-bit Arm
®
Cortex
®
-M0+ MCU, which integrates a specific hardware block called the
HW Processor. The HW Processor can perform 2-channel Voice/Audio playback, Voice Speed Conversion, and
Self Memory Check without using any CPU resource. With the HW Processor, a low memory footprint and multi-
language support are achievable because of its integrated high-compression algorithm for voice and audio. The
S1C31D50/D51 is suitable for home electronics, white goods, and battery-based products, which require a voice
and audio playback function. Furthermore, the S1C31D51 can realize a voice and audio playback function with a
buzzer and a small number of external components without using an external audio amplifier.
Table 1.1.1 Features
S1C31D50/D51 lineup
48-pin package
64-pin package
80-pin package
100-pin package
CPU
CPU core
Arm
®
32-bit RISC CPU core Cortex
®
-M0+
Other
Serial-wire debug ports (SW-DP) and a micro trace buffer (MTB) included
Embedded Flash memory
Capacity
192K bytes (for both instructions and data)
Erase/program count
1,000 times (min.)
*
When being programmed by the dedicated flash loader
Other
On-board programming function
Flash programming voltage can be generated internally.
Embedded RAMs
General-purpose RAM
S1C31D50: 8K bytes
S1C31D51: 10K bytes
Voice RAM
S1C31D50: 14K bytes (Usable as a general-purpose RAM when the HW processor is inactive.)
S1C31D51: 12K bytes (Usable as a general-purpose RAM when the HW processor is inactive.)
Instruction cache
512 bytes
HW processor (HWP)
Sound play function
Sound algorithm
EPSON high quality and high compression algorithm (EOV: EPSON Original Sound Format)
Playback channels
2 channels with mixing supported (e.g. Ch.0: voice, Ch.1: BGM)
Sampling frequency
15.625 kHz
Bitrate
16/24/32/40 kbps
Voice speed conversion
75% to 125% (5% steps)
Sound output
Speaker output (S1C31D50/D51) and buzzer output (S1C31D51)
Memory check function
Embedded RAM check
Read/write check, March-C
Embedded Flash check
Checksum, CRC
External QSPI-Flash check
Checksum, CRC
Sound DAC (SDAC)
Sampling frequency
15.625 kHz
Serial interfaces
UART (UART3)
3 channels
Baud-rate generator included, IrDA1.0 supported
Open drain output, signal polarity, and baud rate division ratio are configurable.
Infrared communication carrier modulation output function
Synchronous serial interface (SPIA)
3 channels
2 to 16-bit variable data length
The 16-bit timer (T16) can be used for the baud-rate generator in master mode.
Quad synchronous serial interface
(QSPI)
1 channel
Supports single, dual, and quad transfer modes.
Low CPU overhead memory mapped access mode that can directly read data from the exter-
nal flash memory with XIP (eXecute-In-Place) mode.
I
2
C (I2C)
3 channels
Baud-rate generator included
DMA controller (DMAC)
Number of channels
4 channels
Data transfer path
Memory to memory, memory to peripheral, and peripheral to memory
Transfer mode
Basic, ping-pong, scatter-gather
DMA trigger source
UART3, SPIA, QSPI, I2C, T16B, ADC12A, and software
Clock generator (CLG)
System clock source
4 sources (IOSC/OSC1/OSC3/EXOSC)
System clock frequency
(operating frequency)
V
D1
voltage mode = mode0: 16 MHz (max.)
V
D1
voltage mode = mode1: 1.8 MHz (max.)