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15 Quad Synchronous Serial Interface (QSPI)
S1C31D50/D51 TECHNICAL MANUAL
Seiko Epson Corporation
15-9
(Rev. 2.00)
Cycle No.
QSPICLKn
QSDIOn3
QSDIOn2
QSDIOn1
QSDIOn0
QSDIOn3
QSDIOn2
QSDIOn1
QSDIOn0
QSDIOn3
QSDIOn2
QSDIOn1
QSDIOn0
QSDIOn3
QSDIOn2
QSDIOn1
QSDIOn0
1
QSPI_nMOD.
LSBFST bit
0
1
2
3
4
Dw15
Dw1
Dr1
Dw11
Dw5
Dr5
Dw7
Dw9
Dr9
Dw3
Dw14
Dr14
Dw10
Dr10
Dw6
Dr6
Dw2
Dr2
Dw0
Dw4
Dw8
Dw12
Dw13
Dr0
Dr4
Dr8
Dr12
Dr13
Dr3
Dr7
Dr11
Dr2
Dr6
Dr10
Dr14
Dr15
Dr15
Dr11
Dr7
Dr3
Dw13
Dw3
Dw9
Dw7
Dw5
Dw11
Dw1
Dw12
Dr12
Dw8
Dr8
Dw4
Dr4
Dw0
Dr0
Dw2
Dw6
Dw10
Dw14
Dw15
Dr13
Dr9
Dr5
Dr1
Writing Dw[15:0] to the QSPI_nTXD register
Loading Dr[15:0] to the QSPI_nRXD register
Figure 15.4.3 Data Format Selection for Quad Transfer Mode Using the QSPI_nMOD.LSBFST Bit
(QSPI_nMOD.TMOD[1:0] bits = 0x2, QSPI_nMOD.CHLN[3:0] bits = 0x3, QSPI_nMOD.CPOL bit = 0, QSPI_nMOD.CPHA bit = 0)
15.5 Operations
15.5.1 Register Access Mode
Data can be read from or written to the external SPI/QSPI device by accessing the registers in both master and slave
modes.
In single transfer mode, transmit data are always output from the QSDIO
n
0 pin and receive data are always input to
the QSDIO
n
1 pin (the QSDIO
n
[3:2] pins are not used). The operations are backward compatible with legacy SPI
(e.g., synchronous serial interface of this MCU).
In dual transfer mode, transmit data are output from the QSDIO
n
[1:0] pins when the transfer direction is set to out-
put (QSPI_
n
CTL.DIR bit = 0). Receive data are input from the QSDIO
n
[1:0] pins when the transfer direction is set
to input (QSPI_
n
CTL.DIR bit = 1). The QSDIO
n
[3:2] pins are not used. The number of data transfer clocks is con-
figured using the QSPI_
n
MOD.CHLN[3:0] bits. Since two data lines are used for data transfer, the data bit length
(number of clocks) is obtained by dividing the number of transfer data bits by two.
In quad transfer mode, transmit data are output from the QSDIO
n
[3:0] pins when the transfer direction is set to
output (QSPI_
n
CTL.DIR bit = 0). Receive data are input from the QSDIO
n
[3:0] pins when the transfer direction
is set to input (QSPI_
n
CTL.DIR bit = 1). The number of data transfer clocks is configured with the QSPI_
n
MOD.
CHLN[3:0] bits. Since four data lines are used for data transfer, the data bit length (number of clocks) is obtained
by dividing the number of transfer data bits by four.