![background image](http://html1.mh-extra.com/html/eaton/edr-3000/edr-3000_installation-operation-and-maintenance-manual_3974052746.webp)
EDR-3000
IM02602003E
Name
Description
Logic.LE37.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE37.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE37.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE37.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE37.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE37.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE38.Gate Out
Signal: Output of the logic gate
Logic.LE38.Timer Out
Signal: Timer Output
Logic.LE38.Out
Signal: Latched Output (Q)
Logic.LE38.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE38.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE38.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE38.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE38.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE38.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE39.Gate Out
Signal: Output of the logic gate
Logic.LE39.Timer Out
Signal: Timer Output
Logic.LE39.Out
Signal: Latched Output (Q)
Logic.LE39.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE39.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE39.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE39.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE39.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE39.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE40.Gate Out
Signal: Output of the logic gate
Logic.LE40.Timer Out
Signal: Timer Output
Logic.LE40.Out
Signal: Latched Output (Q)
Logic.LE40.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE40.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE40.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE40.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE40.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE40.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE41.Gate Out
Signal: Output of the logic gate
Logic.LE41.Timer Out
Signal: Timer Output
Logic.LE41.Out
Signal: Latched Output (Q)
Logic.LE41.Out inverted
Signal: Negated Latched Output (Q NOT)
www.eaton.com
734
Содержание EDR 3000
Страница 2: ......
Страница 4: ......
Страница 6: ......
Страница 7: ...Medium Voltage Switchgear Assembly...
Страница 8: ......
Страница 10: ......
Страница 11: ...Component Data...
Страница 12: ......
Страница 64: ...EDR 3000 IM02602003E Ethernet RJ45 Terminal Marking www eaton com 52 1 8 TxD TxD RxD N C N C RxD N C N C...
Страница 659: ...EDR 3000 IM02602003E Real Time Clock Running Reserve of the Real Time Clock 1 year min www eaton com 647...