![background image](http://html1.mh-extra.com/html/eaton/edr-3000/edr-3000_installation-operation-and-maintenance-manual_3974052748.webp)
EDR-3000
IM02602003E
Name
Description
Logic.LE45.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE45.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE45.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE45.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE46.Gate Out
Signal: Output of the logic gate
Logic.LE46.Timer Out
Signal: Timer Output
Logic.LE46.Out
Signal: Latched Output (Q)
Logic.LE46.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE46.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE46.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE46.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE46.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE46.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE47.Gate Out
Signal: Output of the logic gate
Logic.LE47.Timer Out
Signal: Timer Output
Logic.LE47.Out
Signal: Latched Output (Q)
Logic.LE47.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE47.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE47.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE47.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE47.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE47.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE48.Gate Out
Signal: Output of the logic gate
Logic.LE48.Timer Out
Signal: Timer Output
Logic.LE48.Out
Signal: Latched Output (Q)
Logic.LE48.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE48.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE48.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE48.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE48.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE48.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE49.Gate Out
Signal: Output of the logic gate
Logic.LE49.Timer Out
Signal: Timer Output
Logic.LE49.Out
Signal: Latched Output (Q)
Logic.LE49.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE49.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE49.Gate In2-I
State of the module input: Assignment of the Input Signal
www.eaton.com
736
Содержание EDR 3000
Страница 2: ......
Страница 4: ......
Страница 6: ......
Страница 7: ...Medium Voltage Switchgear Assembly...
Страница 8: ......
Страница 10: ......
Страница 11: ...Component Data...
Страница 12: ......
Страница 64: ...EDR 3000 IM02602003E Ethernet RJ45 Terminal Marking www eaton com 52 1 8 TxD TxD RxD N C N C RxD N C N C...
Страница 659: ...EDR 3000 IM02602003E Real Time Clock Running Reserve of the Real Time Clock 1 year min www eaton com 647...