![background image](http://html1.mh-extra.com/html/eaton/edr-3000/edr-3000_installation-operation-and-maintenance-manual_3974052738.webp)
EDR-3000
IM02602003E
Name
Description
Logic.LE4.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE4.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE4.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE4.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE4.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE5.Gate Out
Signal: Output of the logic gate
Logic.LE5.Timer Out
Signal: Timer Output
Logic.LE5.Out
Signal: Latched Output (Q)
Logic.LE5.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE5.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE5.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE5.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE5.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE5.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE6.Gate Out
Signal: Output of the logic gate
Logic.LE6.Timer Out
Signal: Timer Output
Logic.LE6.Out
Signal: Latched Output (Q)
Logic.LE6.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE6.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE6.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE6.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE6.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE6.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE7.Gate Out
Signal: Output of the logic gate
Logic.LE7.Timer Out
Signal: Timer Output
Logic.LE7.Out
Signal: Latched Output (Q)
Logic.LE7.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE7.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE7.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE7.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE7.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE7.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE8.Gate Out
Signal: Output of the logic gate
Logic.LE8.Timer Out
Signal: Timer Output
Logic.LE8.Out
Signal: Latched Output (Q)
Logic.LE8.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE8.Gate In1-I
State of the module input: Assignment of the Input Signal
www.eaton.com
726
Содержание EDR 3000
Страница 2: ......
Страница 4: ......
Страница 6: ......
Страница 7: ...Medium Voltage Switchgear Assembly...
Страница 8: ......
Страница 10: ......
Страница 11: ...Component Data...
Страница 12: ......
Страница 64: ...EDR 3000 IM02602003E Ethernet RJ45 Terminal Marking www eaton com 52 1 8 TxD TxD RxD N C N C RxD N C N C...
Страница 659: ...EDR 3000 IM02602003E Real Time Clock Running Reserve of the Real Time Clock 1 year min www eaton com 647...