Dini Group DN9002K10PCI, Руководство пользователя

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H A R D W A R E
top-level input to this module (no buffers or flip-flops should be inserted). The FPGA
designer need only be concerned about the signals in the “FPGA INTERFACE” side of the
module.
The user (“FPGA”) interface presents 6 separate interface ports: Target Write, Target Read,
DMA R0, DMA R1, DMA T0, and DMA T1. The Target Write and Target Read interfaces
share BAR and address lines, as target reads and writes cannot happen simultaneously. Each
interface has its own "enable", "accept", and "data" ports. Read interfaces also have a
"data_valid" port. The "enable" signals are held active until the associated "accept" signal goes
active. The "accept" signal for an interface may be tied high if it is guaranteed that transfers for
that interface can be accepted every clock cycle (i.e. if the interface is connected to a block
RAM). "Data_valid" can be pulsed with the "accept" signal, or any time after- this allows reads
to be pipelined.
For the purposes of simulation, a model of the QL5064 is provided. The QL5064 “FPGA”
portion should not be considered part of the user design space, and development on this code
should not be done.
7.1.1 FPGA-initiated DMA
You need to set up the QL5064 DMA engine with the same address and byte-count as your
DMA core, so that the data is passed through both FIFOs seamlessly. For example, if you want
to write a block of data to the PCI bus, you would do the following:
Write PCI address to QL5064 register 0x00 (T0 address)
Write source address to your DMA core
Write byte count to QL5064 register 0x08 (T0 transfer count)
Write byte count to your DMA core
Write a 1 to QL5064 register 0x90 bit 16 (T0 start)
Start your DMA transfer
If you do these steps, your DMA core should start fetching data and send it to the T0 FIFO at
QL5064 register 0xc0. The QL5064 will take whatever data you give it, and use its DMA engine
to write it to the address you chose. You may want to set up a hardware wrapper with a state
machine that will accept DMA information from your core and automatically route it to the
correct QL5064 registers, so that you don't need to change any software. This is what I meant
by glue logic, in my previous email.
The alternative to this method is to use SPCI transfers, which is a way to set up a single PCI
write or read in the QL5064. This is much slower, but it requires fewer QL5064 control
registers to be accessed, and gives you more direct control over the transfers sent to the PCI
bus. The register descriptions needed for either option are in the manual that I attached with
my previous email.
DN9002K10PCI User Guide www.dinigroup.com 82