Dini Group DN9002K10PCI, Руководство пользователя

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H A R D W A R E
clock driver. Details on how to implement a DDR2 controller are in the Xilinx application note
XAPP858. You can also see the provided DDR2 reference design for example code.
A basic block diagram of the clocking is given below.
Note that the DIMM_CK2 signal is driven by the FPGA from a 1.8V bank. The output should
be a DIFF_SSTL18. It is received by a global clock (“GC”) pin on the Virtex-4 device. To
receive the signal, use an LVDS_EXT input with DIFF_TERM attribute set to TRUE.
The CK0, CK1 and CK2 signals are length-matched, so this input should be synchronous to the
clock input of the DIMM module.
The DQ and DM signals are synchronous to the DQS signals in each bank. See the DDR2
SODIMM module specification for information on the timing of this interface.
DQS timing
In order to clock the DQ and DM inputs using the DQS signal, you must use a BUFIO clock
buffer on the DQS signal.
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