Dini Group DN9002K10PCI, Руководство пользователя

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H A R D W A R E
16.3.3 Timing
The length matching of the DDR2 interface signals includes all signals except for DIMM_SCL
and DIMM_SDA signals.
Due to the source-synchronous clocking techniques used by the DDR2 interface, the delay
from FPGA to DIMM should not be needed, but is provided here anyway.
DIMMB
Length
90mm
Delay
510ps
The trace impedance to each of the connectors is controlled to 50-ohms. All signals in the
interface are ground-referenced. Note that this is contradictory to the recommendations of the
DDR2 SODIMM specification.
To increase the setup time available for control signals, modules may be set into T2 mode. In
the reference design, the modules are in T1 mode.
Address Control signals:
FPGA:
Assume a DCM in system-synchronous mode.
Worst clock-to-out time of Virtex 5: 3.37 with DCM. No phase-shift.
Worst setup time: 0.097
Worst hold time: 0.21
DIMM:
Setup 600ps
Hold 600ps
DQ signals:
DIMM:
DQS must be within 350ps of DQ, DM
setup 400ps
Hold 400ps
FPGA:
IDELAY
setup –1.23
hold 2.14
clock-to-out 5.34
16.4 Compatible Modules
The DDR2 interfaces are compatible with standard PC2-2700 or faster memory modules up to
a capacity of 4GB. The greatest capacity modules available at print time are 2GB. The interface
has been tested with modules with a CAS latency of 3. The interface is characterized to 250Mhz,
DN9002K10PCI User Guide www.dinigroup.com 103