Dini Group DN9002K10PCI, Руководство пользователя

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H A R D W A R E
18.1.2 Electrical
The MB signals are fixed at a 2.5V signaling level. LVCMOS25 is an appropriate singling
standard. Due to very heavy capacitive loads on the MB signals, you must use drive strength of
24mA to use main bus. DCI should not be used because the signals are not impedance-
controlled. Although not required, by convention, data on the MB signals is synchronous to the
MB48 clock. In order to use the “Main Bus” interface to communicate with USB or PCI, you
must use the MB48 clock. This clock runs at a fixed 48Mhz.
Note that as well as the 36 “MB” signals, there are also 16 signals in the “Selectmap_D[15:0]”
that connect to all FPGAs that could be used for user data. Dini Group does not directly
support using these signals. If you chose to use these signals, note that the FPGA design can
interfere with the programming of FPGAs. You would have to keep the outputs on these
signals tri-stated until all FPGA configurations are complete.
18.1.3 Timing
As described above, the MB signals are typically run synchronous to the 48Mhz MB48 bus. This
is the highest speed that the MB signals are guaranteed to run using a system-synchronous
clocking method. You may be able to achieve performance from FPGA-to-FPGA on this bus
as high as 75Mhz, if you adjust input and output clocks and perform a timing analysis. Using
LVCMOS25 with a drive strength of 24mA, you can assume there is a 10ns rise time/flight time
for signals on this bus.
No length matching is done on the MB signals.
Virtex 5 clock-to-out time: 3.37ns with DCM
Virtex 5 setup time: 0.97ns
Flight time: 10ns (includes rise-time adjustment for capacitive load)
Total: 14.34ns (69 MHz)
The MB* signals are tested at 48 MHz
18.2 Error Codes
The Main Bus interface has no way of signaling an error condition on read requests, but some
errors will result in the same sentinel values being returned. Following is a list of these values.
0xABCDABCD: The Main Bus read timed out. (PCI only)
0xDEADDEAD: The Main Bus read times out (USB only). When this condition occurs, a
register, accessible as part of the “configuration register” space, gets incremented. In this way, it
is possible for a Main Bus access program to verify that a MainBus transaction has succeeded.
0xFFFFFFFF: The PCI bus timed out. This is not a value returned by the DN9002K10PCI.
The PCI request was not returned. The QL5064 may not be configured correctly.
0xDEAD5566: This value is returned by the Dini Group reference design as a default value,
when a read request is to an address that has no registers associated with it.
DN9002K10PCI User Guide www.dinigroup.com 108