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C O N T R O L L E R S O F T W A R E
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Reset
this command asserts the RESET# signal to all FPGAs simultaneously. This is the
same signal that is asserted when the user hits the “Soft Reset” (User Reset) button.
Its function in the user design is left for the user to define. In the reference design, it
causes a global, asynchronous reset. This option also causes the SYS_RSTn signal
on the daughtercards to be asserted.
1.2.4
FPGA Reference Design
•
Single Ended Interconnect Test (slow)
this menu option will run test single ended test on which FPGA is configured.
•
Read FPGA Clock Frequencies
This menu option measures and reads back the frequencies of the eight global clock
networks, and displays them on the message log.
•
Read DDR I2C Data
This menu option read back DDR2 information
1.2.5
Main Bus
The way that user FPGA designs can communicate over USB is the “Main Bus” interface. The
“Reference design” menu uses the main bus to read and write registers in the reference design to
control the board tests. These tests can be done by the using these menu options without the
user having to understand the Main Bus interface or the main bus memory space and it’s
mapping to the reference design. The Main Bus menu allows direct control of the Main Bus.
This can be useful if you are using your own FPGA core that implements the main bus.
•
Write and Read DWORD
this displays a dialog box for writing and reading to the Main Bus address space. It
includes some debugging features. All main bus transactions are of length 4 bytes
(DWORD)
•
Test Address Space
This writes and reads random data to the address range specified in a dialog box, and
prints and error message when the read and write do not match.
•
Read Address Space to file
this reads data from the main bus at the address specified, and writes the data to a binary
file specified. Data on the main bus is in little-endian order. The address after each
DWORD is implicitly incremented. This behavior can be turned off (contact support)
•
Write Address space from file
this reads data from a file and writes the data to the address on main bus specified. The
data is written in little-endian order. The address is implicitly incremented after each
DWORD of data. This behavior can be changed (contact support)
DN9002K10PCI User Guide
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