Dini Group DN9002K10PCI, Руководство пользователя

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Q U I C K S T A R T G U I D E
you to select the configuration file to use for configuration. Browse to the provided user’s CD
“D:\FPGA_Reference_Designs\Programming_Files\DN9002K10PCI\MainTest\LX330\fpg
a_a.bit”
If you are configuring an LX220 or LX110 device you should select a bit file from the LX220 or
LX110 directories instead. Failing to select the correct type of bit file will result in the USB
Controller program to warn you, and the FPGA fail to configure. The program will report the
status of the configuration when it finishes. “DONE did not go high”. This refers to the
DONE selectMap signal, which is asserted by the FPGA when it is properly configured.
If you are configuring FPGA B or FPGA C, you should select fpga_b.bit or fpga_c.bit instead.
Should you configure the wrong FPGA with the wrong bitfile, the FPGA will succeed to
configure, but probably won’t function properly. This is not recommended because it could lead
to bus contension and excessive heat generation.
Done
FPGA B cleared successfully.
FPGA A cleared successfully.
Doing a sanity check...Sanity Check passed. Configuring FPGA
B via USB...please wait.
File
D:\\dn_BitFiles\DN9002K10PCI\MainTest\LX330\fpga_b.bit
transferred.
Configured FPGA B via USB
Figure 6 USB Controller Log Output
The message box below the DN9002K10PCI graphic should display some information about
the configuration process. When the configuration is successful, the green LED should re-
appear next to the FPGA.
5.2.2 Set Clock Frequencies
To change the clock frequencies of G0, G1 or G2, select the “Clock settings” option from the
“Settings” menu.
A dialog box appears asking to which frequency you would like to set each clock. Enter 350,
200, 200 for G0, G1 and G2 respectively. The log window will display feedback including what
frequencies the clocks were set to. The actual frequency to which each clock is set may differ
from the frequency you entered because the frequency synthesizers have a limited granularity.
5.2.3 Run Hardware Test (DDR2)
First, hit the “Enable USB->FPGA communication” button. This must be done before the
program can interact with the reference design. You must also have the reference design loaded,
and a DDR2 module installed in a memory socket connected to the FPGA using that reference
design. Also, the clock settings must be correct. Follow the procedure in the previous section to
accomplish this.
DN9002K10PCI User Guide www.dinigroup.com 17